TLV713

TLV713P

SBVS195D – SEPTEMBER 2012 – REVISED JULY 2013

www.ti.com

APPLICATION INFORMATION

The TLV713 belongs to a new family of next-generation value low-dropout (LDO) regulators. These devices

consume low quiescent current and deliver excellent line and load transient performance. These characteristics,

RF portable applications.

This family of regulators offers current limit and thermal protection. Device operating junction temperature is

–40°C to +85°C.

INPUT AND OUTPUT CAPACITOR CONSIDERATIONS

The TLV713 uses an advanced internal control loop to obtain stable operation both with and without the use of

input or output capacitors. The TLV713xx dynamic performance is improved with the use of an output capacitor.

An output capacitance of 0.1

μF or larger generally provides good dynamic response. X5R- and X7R-type

ceramic capacitors are recommended because these capacitors have minimal variation in value and equivalent

series resistance (ESR) over temperature.

Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-µF to

1-µF capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient

response, input ripple, and PSRR. An input capacitor is recommended if the source impedance is more than

0.5

Ω. A higher-value capacitor may be necessary if large, fast, rise-time load transients are anticipated or if the

device is located several inches from the input power source.

BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE

Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance

(such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate

output capacitor ground connection should be connected directly to the device GND pin. High ESR capacitors

may degrade PSRR performance.

INTERNAL CURRENT LIMIT

The TLV713 has an internal foldback current limit that helps protect the regulator during fault conditions. The

current supplied by the device is gradually throttled down while the output voltage decreases. When the output is

shorted, the LDO supplies a typical current of 40 mA. Output voltage is not regulated when the device is in

thermal shutdown is triggered and the device turns off. While the device cools down, it is turned on by the

internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and

thermal shutdown. See the Thermal Information section for more details.

The TLV713 PMOS pass element has a built-in body diode that conducts current when the voltage at OUT

exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated,

external limiting to 5% of the rated output current is recommended.

SHUTDOWN

The enable pin (EN) is active high. The device is enabled when the voltage at the EN pin goes above 0.9 V. This

relatively lower voltage value required to turn the LDO on can be exploited to power the LDO with a GPIO of

recent processors whose GPIO logic 1 voltage level is lower than traditional microcontrollers. The device is

turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be

connected to the IN pin.

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