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LT1675 Datasheet(PDF) 8 Page - Linear Technology |
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LT1675 Datasheet(HTML) 8 Page - Linear Technology |
8 / 16 page LT6555 8 6555f Power Supplies The LT6555 is optimized for ±5V supplies but can be operated on as little as ±2.25V or a single 4.5V supply and as much as ±6V or a single 12V supply. Internally, each supply is independent to improve channel isolation. Do not leave any supply pins disconnected or the part may not function correctly! Enable/Shutdown The LT6555 has a shutdown mode controlled by the EN pin and referenced to the DGND pin. If the amplifier will be enabled at all times, the EN pin can be connected directly to DGND. If the enable function is desired, either driving the pin above 2V or allowing the internal 46k pull- up resistor to pull the EN pin to the top rail will disable the amplifier. When disabled, the DC output impedance will rise to approximately 360 Ω through the internal feedback and gain resistors. Supply current into the amplifier in the disabled state will be: I VV k VV k S EN =+ + + – – – 46 80 It is important that the following constraints on the DGND, EN and SEL pins are always followed: V+ – VDGND ≥ 4.5V VEN – VDGND ≤ 5.5V VSEL – VDGND ≤ 8V In dual supply cases where V+ is less than 4.5V, DGND should be connected to a potential below ground, such as V–. Since the EN and SEL pins are referenced to DGND, they may need to be pulled below ground in those cases. In single supply applications above 5.5V, an additional resistor may be needed from the EN pin to DGND if the pin is ever allowed to float. For example, on a 12V single supply, a 33k resistor would protect the pin from floating too high while still allowing the internal pull-up resistor to disable the part. On dual ±2.25V supplies, connecting the DGND pin to V– is the only way of ensuring that V+ – VDGND ≥ 4.5V. The DGND pin should not be pulled above the EN pin since doing so will turn on an ESD protection diode. If the EN pin voltage is forced a diode drop below the DGND pin, current should be limited to 10mA or less. The enable/disable times of the LT6555 are fast when driven with a logic input. Turn on (from 50% EN input to 50% output) typically occurs in less than 50ns. Turn off is slower, but is typically below 500ns. Channel Select The SEL pin uses the same internal threshold as the EN pin and is also referenced to DGND. When the pin is logic low, the channel A inputs are passed to the output. When the pin is logic high, the channel B inputs are passed to the output. The pin should not be floated but can be tied to DGND to force the outputs to always be channel A or to V+ (when less than 8V) to force the outputs to always be channel B. Truth Table SEL A/B EN OUT 00 2 × IN A 10 2 × IN B X 1 OFF Input Considerations The LT6555 uses input clamps referenced to the VREF pin to prevent damage to the input stage on the unselected channel. Three transistors in series limit the input voltage to within three diode drops ( ±) from VREF. VREF is nomi- nally set to half of the sum of the supplies by the 40k resistors. A simplified schematic is shown in Figure 1. To improve clamping, the pin’s DC impedance should be minimized by connecting the VREF pin directly to ground in the symmetric dual supply case with a common mode voltage of 0V. While loaded output swing limits the useful input voltage range in that case, if the common mode voltage is not centered at ground or the input voltage exceeds plus or minus three diodes from ground, an external resistor to either supply can be added to shift the APPLICATIO S I FOR ATIO |
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