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ADSP-BF607 Datasheet(PDF) 6 Page - Analog Devices |
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ADSP-BF607 Datasheet(HTML) 6 Page - Analog Devices |
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6 / 112 page  Rev. 0 | Page 6 of 112 | June 2013 ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Event Handling The processor provides event handling that supports both nest- ing and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher-priority event takes precedence over ser- vicing of a lower-priority event. The processor provides support for five different types of events: • Emulation – An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. • Reset – This event resets the processor. • Nonmaskable Interrupt (NMI) – The NMI event can be generated either by the software watchdog timer, by the NMI input signal to the processor, or by software. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system. • Exceptions – Events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts – Events that occur asynchronously to program flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest-priority interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers. For more information, see the ADSP-BF60x Processor Programmer’s Reference. System Event Controller (SEC) The SEC manages the enabling, prioritization, and routing of events from each system interrupt or fault source. Additionally, it provides notification and identification of the highest priority active system interrupt request to each core and routes system fault sources to its integrated fault management unit. Trigger Routing Unit (TRU) The TRU provides system-level sequence control without core intervention. The TRU maps trigger masters (generators of trig- gers) to trigger slaves (receivers of triggers). Slave endpoints can be configured to respond to triggers in various ways. Common applications enabled by the TRU include: • Automatically triggering the start of a DMA sequence after a sequence from another DMA channel completes •Software triggering • Synchronization of concurrent activities Pin Interrupts Every port pin on the processor can request interrupts in either an edge-sensitive or a level-sensitive manner with programma- ble polarity. Interrupt functionality is decoupled from GPIO operation. Six system-level interrupt channels (PINT0–5) are reserved for this purpose. Each of these interrupt channels can manage up to 32 interrupt pins. The assignment from pin to interrupt is not performed on a pin-by-pin basis. Rather, groups of eight pins (half ports) can be flexibly assigned to interrupt channels. Every pin interrupt channel features a special set of 32-bit mem- ory-mapped registers that enable half-port assignment and interrupt management. This includes masking, identification, and clearing of requests. These registers also enable access to the respective pin states and use of the interrupt latches, regardless of whether the interrupt is masked or not. Most control registers feature multiple MMR address entries to write-one-to-set or write-one-to-clear them individually. General-Purpose I/O (GPIO) Each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers: • GPIO direction control register – Specifies the direction of each individual GPIO pin as input or output. • GPIO control and status registers – A “write one to mod- ify” mechanism allows any combination of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO pins. • GPIO interrupt mask registers – Allow each individual GPIO pin to function as an interrupt to the processor. GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. • GPIO interrupt sensitivity registers – Specify whether indi- vidual pins are level- or edge-sensitive and specify—if edge-sensitive—whether just the rising edge or both the ris- ing and falling edges of the signal are significant. Pin Multiplexing The processor supports a flexible multiplexing scheme that mul- tiplexes the GPIO pins with various peripherals. A maximum of 4 peripherals plus GPIO functionality is shared by each GPIO pin. All GPIO pins have a bypass path feature – that is, when the output enable and the input enable of a GPIO pin are both active, the data signal before the pad driver is looped back to the receive path for the same GPIO pin. For more information, see GP I/O Multiplexing for 349-Ball CSP_BGA on Page 33. MEMORY ARCHITECTURE The processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency core-accessible memory as cache or SRAM, and larger, lower-cost and performance interface-acces- sible memory systems. See Figure 3 and Figure 4. |
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