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ADSP-BF608 Datasheet(PDF) 1 Page - Analog Devices |
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ADSP-BF608 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 112 page  Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Blackfin Dual Core Embedded Processor ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Dual-core symmetric high-performance Blackfin processor, up to 500 MHz per core Each core contains two 16-bit MACs, two 40-bit ALUs, and a 40-bit barrel shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Pipelined Vision Processor provides hardware to process sig- nal and image algorithms used for pre- and co-processing of video frames in ADAS or other video processing applications Accepts a range of supply voltages for I/O operation. See Operating Conditions on Page 52 Off-chip voltage regulator interface 349-ball BGA package (19 mm × 19 mm), RoHS compliant MEMORY Each core contains 148K bytes of L1 SRAM memory (proces- sor core-accessible) with multi-parity bit protection Up to 256K bytes of L2 SRAM memory with ECC protection Dynamic memory controller provides 16-bit interface to a single bank of DDR2 or LPDDR DRAM devices Static memory controller with asynchronous memory inter- face that supports 8-bit and 16-bit memories 4 Memory-to-memory DMA streams, 2 of which feature CRC protection Flexible booting options from flash, SD EMMC and SPI mem- ories and from SPI, link port and UART hosts Memory management unit provides memory protection Figure 1. Processor Block Diagram SYSTEM CONTROL BLOCKS PERIPHERALS HARDWARE FUNCTIONS EXTERNAL BUS INTERFACES LPDDR DDR2 CRC PIPELINED VISION PROCESSOR PIXEL COMPOSITOR DMA SYSTEM 3× PPI 4× LINK PORT 2× EMAC WITH 2× IEEE 1588 EMMC/RSI 3× SPORT 2× SPI 2× UART 1× CAN 8× TIMER 2× PWM 1× COUNTER 2× TWI USB 2.0 HS OTG L2 MEMORY 256K BYTE ECC- PROTECTED SRAM 32K BYTE ROM 112 GP I/O FLASH SRAM EMULATOR TEST & CONTROL PLL & POWER MANAGEMENT FAULT MANAGEMENT EVENT CONTROL DUAL WATCHDOG CORE 1 148K BYTE PARITY BIT PROTECTED L1 SRAM INSTRUCTION/DATA B 1× ACM 16 16 DYNAMIC MEMORY CONTROLLER STATIC MEMORY CONTROLLER VIDEO SUBSYSTEM CORE 0 148K BYTE PARITY BIT PROTECTED L1 SRAM INSTRUCTION/DATA B |
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