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AD5232BRU10 Datasheet(PDF) 5 Page - Analog Devices |
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AD5232BRU10 Datasheet(HTML) 5 Page - Analog Devices |
5 / 24 page Data Sheet AD5232 Rev. C | Page 5 of 24 INTERFACE TIMING CHARACTERISTICS All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and are timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V. Table 2. Parameter1, 2 Symbol Conditions Min Typ3 Max Unit Clock Cycle Time (tCYC) t1 20 ns CS Setup Time t2 10 ns CLK Shutdown Time to CS Rise t3 1 tCYC Input Clock Pulse Width t4, t5 Clock level high or low 10 ns Data Setup Time t6 From positive CLK transition 5 ns Data Hold Time t7 From positive CLK transition 5 ns CS to SDO-SPI Line Acquire t8 40 ns CS to SDO-SPI Line Release t9 50 ns CLK to SDO Propagation Delay4 t10 RP = 2.2 kΩ, CL < 20 pF 50 ns CLK to SDO Data Hold Time t11 RP = 2.2 kΩ, CL < 20 pF 0 ns CS High Pulse Width5 t12 10 ns CS High to CS High5 t13 4 tCYC RDY Rise to CS Fall t14 0 ns CS Rise to RDY Fall Time t15 0.15 0.3 ms Store/Read EEMEM Time6 t16 Applies to Command Instruction 2, Command Instruction 3, and Command Instruction 9 25 ms CS Rise to Clock Rise/Fall Setup t17 10 ns Preset Pulse Width (Asynchronous) tPRW Not shown in timing diagram 50 ns Preset Response Time to RDY High tPRESP PR pulsed low to refresh wiper positions 70 µs 1 Guaranteed by design; not subject to production test. 2 See the Timing Diagrams section for the location of measured values. 3 Typicals represent average readings at 25°C and VDD = 5 V. 4 Propagation delay depends on the value of VDD, RPULL-UP, and CL. 5 Valid for commands that do not activate the RDY pin. 6 RDY pin low only for Command Instruction 2, Command Instruction 3, Command Instruction 8, Command Instruction 9, Command Instruction 10, and the PR hardware pulse: CMD_8 ~ 1 ms, CMD_9 = CMD_10 ~ 0.12 ms, and CMD_2 = CMD_3 ~ 20 ms. Device operation at TA = −40°C and VDD < 3 V extends the save time to 35 ms. |
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