SN65LBC031, SN65LBC031Q, SN75LBC031

HIGH-SPEED CONTROLLER AREA NETWORK (CAN) TRANSCEIVERS

SLRS048A – MAY 1998 – REVISED APRIL 2000

5

POST OFFICE BOX 655303

transmitter electrical characteristics over recommended ranges of supply and operating free-air

temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VO(CANHR)

VO(CANLR)

Output voltage (recessive state)

See Figure 2,

S1 open

2

0.5VCC

3

V

VO(DIFFR)

Differential output voltage (recessive state)

g,

–500

0

50

mV

VO(CANHD) Output voltage (dominant state)

2.75

3.5

4.5

VO(CANLD)

Output voltage (dominant state)

See Figure 2,

S1 closed

0.5

1.5

2.25

V

VO(DIFFD)

Differential output voltage (dominant state)

1.5

2

3

IIH(TX)

High level input current (TX)

VIH = 2.4 V

–100

–185

µA

IIH(TX)

High-level input current (TX)

VIH = VCC

±2

µA

IIH(ASC)

High level input current (ASC)

VIH = 2.4 V

100

165

µA

IIH(ASC)

High-level input current (ASC)

VIH = VCC

200

340

µA

IIL(TX)

Low-level input current (TX)

VIL = 0.4 V

–180

–400

µA

IIL(ASC)

Low-level input current (ASC)

VIL = 0.4 V

15

25

µA

CI(TX)

TX input capacitance

8

pF

IO(ssH)

CANH short circuit output current

VO(CANH) = –2 V to 20 V

–95

–200

mA

IO(ssL)

CANL short circuit output current

VO(CANL) = 20 V to –2 V

140

250

mA

NOTE 2: All voltage values, except differential bus voltage, are measured with respect to the ground terminal.

transceiver dynamic characteristics over recommended operating free-air temperature range and

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t(l

)

Loop time

See Figures 2 and 3,

S1 closed,

VI(ASC) = 0 V or open circuit,

S2 open

280

ns

t(loop)

Loop time

See Figures 2 and 3,

S1 closed,

VI(ASC) = VCC,

S2 closed

400

ns

SR(RD)

Differential-output slew rate

See Figures 2 and 4,

S1 closed,

VI(ASC) = 0 or open circuit,

S2 open

35

V/

µs

SR(RD)

(recessive to dominant)

See Figures 2 and 4,

S1 closed,

VI(ASC) = VCC,

S2 closed

10

V/

µs

SR(DR)

Differential-output slew rate

See Figures 2 and 4,

S1 closed,

VI(ASC) = 0 or open circuit,

S2 open

10

V/

µs

SR(DR)

(dominant to recessive)

See Figures 2 and 4,

S1 closed,

VI(ASC) = VCC,

S2 closed

10

V/

µs

td(RD)

Differential output delay time

See Figure 2

S1 closed

55

ns

td(DR)

Differential-output delay time

See Figure 2,

S1 closed

160

ns

tpd(RECRD)

Receiver propagation delay

See Figures 2 and 5

90

ns

tpd(RECDR)

gy

time

See Figures 2 and 5

55

ns

NOTE 4: Receiver input pulse width should be >50 ns. Input pulses of <30 ns are suppressed.