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APL3513QBI-TRG Datasheet(PDF) 11 Page - Anpec Electronics Coropration |
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APL3513QBI-TRG Datasheet(HTML) 11 Page - Anpec Electronics Coropration |
11 / 16 page Copyright © ANPEC Electronics Corp. Rev. A.2 - May., 2010 APL3513 www.anpec.com.tw 11 Application Information Input Capacitor A 1 µF ceramic bypass capacitor from V IN to GND, located near the APL3513, is strongly recommended to suppress the ringing during short circuit fault event. Without the bypass capacitor, the output short may cause sufficient ringing on the input (from supply lead inductance) to dam- age internal control circuitry. Output Capacitor A bypassing 0.1 µF ceramic capacitor improves the immu- nity of the device to short-circuit transients. A low-ESR high capacitance between V OUT and GND is suggested to reduce the voltage droop during load transient. Layout Consideration The PCB layout should be carefully performed to maxi- mize thermal dissipation and to minimize voltage drop, droop and EMI. The following guidelines must be considered: 1. Please place the input capacitors near the VIN pin as close as possible. 2. Output decoupling capacitors for load must be placed near the load as close as possible for decoupling high- frequency ripples. 3. Locate APL3513 and output capacitors near the load to reduce parasitic resistance and inductance for excel- lent load transient performance. 4. The negative pins of the input and output capacitors and the GND pin must be connected to the ground plane of the load. 5. Keep V IN and VOUT traces as wide and short as possible. |
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