A43E8332G-95I datasheet(9/42 Pages) AMICC

Part #	A43E8332G-95I

Description	1M X 16 Bit X 4 Banks Synchronous DRAM

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Manufacturer	AMICC [AMIC Technology]

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A43L2616B

(December, 2009, Version 1.3)

8

AMIC Technology, Corp.

Simplified Truth Table

Command

CKEn-1 CKEn

CS

RAS CAS

WE

DQM BA0

BA1

A10

/AP

A9~A0,

A11

Notes

Register

Mode Register Set

H

X

L

X

OP CODE

1,2

Auto Refresh

H

3

Entry

H

L

H

X

3

L

H

3

Refresh

Self

Refresh

Exit

L

H

X

3

Bank Active & Row Addr.

H

X

L

H

X

V

Row Addr.

4

Auto Precharge Disable

L

4

Read &

Column Addr. Auto Precharge Enable

H

X

L

H

L

H

X

V

H

Column

Addr.

4,5

Auto Precharge Disable

L

4

Write &

Column Addr. Auto Precharge Enable

H

X

L

H

L

X

V

H

Column

Addr.

4,5

Burst Stop

H

X

L

H

L

X

Bank Selection

V

L

Precharge

Both Banks

H

X

L

H

L

X

H

X

L

H

Entry

H

L

H

X

Clock Suspend or

Active Power Down

Exit

L

H

X

L

H

Entry

H

L

H

X

L

V

Precharge Power Down Mode

Exit

L

H

X

DQM

H

X

V

X

6

L

H

No Operation Command

H

X

H

X

(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)

Note :

1. OP Code: Operand Code

A0~A11, BA0, BA1: Program keys. (@MRS)

2. MRS can be issued only at both banks precharge state.

A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions as same as CBR refresh of DRAM.

The automatical precharge without Row precharge command is meant by “Auto”.

Auto/Self refresh can be issued only at both precharge state.

4. BA0, BA1 : Bank select address.

If both BA1 and BA0 are “Low” at read, write, row active and precharge, bank A is selected.

If both BA1 is “Low” and BA0 is “High” at read, write, row active and precharge, bank B is selected.

If both BA1 is “High” and BA0 is “Low” at read, write, row active and precharge, bank C is selected.

If both BA1 and BA0 are “High” at read, write, row active and precharge, bank D is selected.

If A10/AP is “High” at row precharge, BA1 and BA0 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read write command cannot be issued.

Another bank read write command can be issued at every burst length.

6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0) but

masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)

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