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74LVC821APW Datasheet(PDF) 10 Page - List of Unclassifed Manufacturers |
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10 / 20 page 9397 750 13276 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 03 — 11 May 2004 10 of 20 Philips Semiconductors 74LVC821A 10-bit D-type flip-flop with 5 V tolerant inputs/outputs [1] All typical values are measured Tamb =25 °C. [2] These typical values are measured at VCC = 3.3 V. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ (CL × VCC2 × fo) = sum of the outputs. [5] The condition is VI = GND to VCC. Tamb = −40 °C to +125 °C tPHL, tPLH propagation delay CP to Qn see Figure 7 VCC = 1.2 V - - - ns VCC = 2.7 V 1.5 - 11.0 ns VCC = 3.0 V to 3.6 V 1.5 - 9.5 ns tPZH, tPZL 3-state output enable time OE to Qn see Figure 9 VCC = 1.2 V - - - ns VCC = 2.7 V 1.5 - 11.0 ns VCC = 3.0 V to 3.6 V 1.3 - 9.5 ns tPHZ, tPLZ 3-state output disable time OE to Qn see Figure 9 VCC = 1.2 V - - - ns VCC = 2.7 V 1.5 - 8.5 ns VCC = 3.0 V to 3.6 V 1.5 - 8.0 ns tW clock pulse width HIGH or LOW see Figure 7 VCC = 1.2 V - - - ns VCC = 2.7 V 3.3 - - ns VCC = 3.0 V to 3.6 V 3.3 - - ns tsu set-up time Dn to CP see Figure 8 VCC = 1.2 V - - - ns VCC = 2.7 V 0.9 - - ns VCC = 3.0 V to 3.6 V 1.9 - - ns th hold time Dn to CP see Figure 8 VCC = 1.2 V - - - ns VCC = 2.7 V 1.5 - - ns VCC = 3.0 V to 3.6 V 1.5 - - ns fmax maximum clock frequency see Figure 7 VCC = 1.2 V - - - MHz VCC = 2.7 V 150 - - MHz VCC = 3.0 V to 3.6 V 150 - - MHz tsk(0) skew VCC = 3.0 V to 3.6 V [3] - - 1.0 ns Table 8: Dynamic characteristics …continued GND = 0 V; tr =tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω; for test circuit see Figure 10 Symbol Parameter Conditions Min Typ Max Unit |
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