SPIRIT1QTR datasheet(8/101 Pages) ETC2

Part #	SPIRIT1QTR

Description	Low data rate, low power sub-1GHZ transceiver

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Introduction

SPIRIT1

8/101

DocID022758 Rev 5

2

Introduction

A simplified block diagram of the SPIRIT1 is shown in

Figure 1.

Figure 1. SPIRIT1 block diagram

The receiver architecture is low-IF conversion. The received RF signal is amplified by a two-

stage low-noise amplifier (LNA) and down-converted in quadrature (I and Q) to the

intermediate frequency (IF). LNA and IF amplifiers make up the RX front-end (RXFE) and

have programmable gain. At IF, I/Q signals are digitized by ADCs. The demodulated data is

then provided to an external MCU either through the 96-byte RX FIFO, readable via SPI, or

directly using a programmable GPIO pin. A 128-bit AES co-processor is available to perform

(offline) data encryption/decryption to secure data transfer.

The transmitter part of the SPIRIT1 is based on direct synthesis of the RF frequency. The

power amplifier (PA) input is the LO generated by the RF synthesizer, while the output level

can be configured between -30 dBm and +11 dBm in 0.5 dB steps. The data to be

transmitted can be provided by an external MCU either through the 96-byte TX FIFO

writable via SPI, or directly using a programmable GPIO pin. The SPIRIT1 supports

frequency hopping, TX/RX and antenna diversity switch control, extending the link range

and improving performance.

The SPIRIT1 has a very efficient power management (PM) system.

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