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ADV7282WBCPZ-M Datasheet(PDF) 6 Page - Analog Devices

Part # ADV7282WBCPZ-M
Description  10-Bit, 4 Oversampled SDTV Video Decoder with Differential Inputs and Deinterlacer
Download  32 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV7282WBCPZ-M Datasheet(HTML) 6 Page - Analog Devices

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ADV7282
Data Sheet
Rev. A | Page 6 of 32
ANALOG SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization. Note that MVDD only applies to the ADV7282-M.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
CLAMP CIRCUITRY
External Clamp Capacitor
0.1
µF
Input Impedance
Clamps switched off
10
MΩ
Large Clamp Source Current
0.4
mA
Large Clamp Sink Current
0.4
mA
Fine Clamp Source Current
10
µA
Fine Clamp Sink Current
10
µA
CLOCK AND I2C TIMING SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization. Note that MVDD only applies to the ADV7282-M.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
28.63636
MHz
Frequency Stability
±50
ppm
I2C PORT
SCLK Frequency
400
kHz
SCLK Minimum Pulse Width High
t1
0.6
µs
SCLK Minimum Pulse Width Low
t2
1.3
µs
Hold Time (Start Condition)
t3
0.6
µs
Setup Time (Start Condition)
t4
0.6
µs
SDATA Setup Time
t5
100
ns
SCLK and SDATA Rise Times
t6
300
ns
SCLK and SDATA Fall Times
t7
300
ns
Setup Time (Stop Condition)
t8
0.6
µs
RESET INPUT
RESET Pulse Width
5
ms
SDATA
SCLK
t3
t5
t3
t4
t8
t6
t7
t2
t1
Figure 3. I2C Timing Diagram


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