ADV7282

Data Sheet

Rev. A | Page 8 of 32

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

Rise Time, 20% to 80%

0.15

0.3 × UI

ns

Fall Time, 80% to 20%

0.15

0.3 × UI

ns

High Speed to Low Power Transition

Stage

Time that the ADV7282-M drives the

flipped last data bit after sending

the last payload data bit of an HS

transmission burst

60 + (4 × UI)

ns

Post-end-of-transmission rise time

(30% to 85%)

35

ns

power state following an HS

transmission burst

105 + (12 × UI)

ns

Time that a low power state is

transmitted after an HS transmis-

sion burst

100

ns

CLOCK LANE HS TX SIGNALING

REQUIREMENTS

See Figure 4

Low Power to High Speed Transition

Stage2

50

ns

Time that the CLKP and CLKN pins

38

95

ns

Clock HS-zero period

300

500

ns

High Speed Differential Voltage Swing

140

200

270

mV p-p

Differential Voltage Mismatch

10

mV

Single-Ended Output High Voltages

360

mV

Static Common-Mode Voltage Level

150

200

250

mV

Static Common-Mode Voltage Mismatch

5

mV

Dynamic Common Level Variations

50 MHz to 450 MHz

25

mV

Above 450 MHz

15

mV

Rise Time, 20% to 80%

0.15

0.3 × UI

ns

Fall Time, 80% to 20%

0.15

0.3 × UI

ns

HS TX CLOCK TO DATA LANE TIMING

REQUIREMENTS

Data to Clock Skew

0.35 × UI

0.65 × UI

ns

1

2

The clock lane remains in high speed mode throughout normal operation. These results apply only to the ADV7282-M during startup.

CLKP/CLKN

D0P/D0N

TRANSMIT FIRST

DATA BIT

LOW POWER

TO

HIGH SPEED

TRANSITION

START OF

TRANSMISSION

SEQUENCE

HIGH SPEED DATA

TRANSMISSION

HS-ZERO

HS-TRAIL

HIGH SPEED

TO

LOW POWER

TRANSITION

Figure 4. ADV7282-M Output Timing Diagram (Conforms with MIPI CSI-2 Specification)