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AD5392BCPZ-3 Datasheet(PDF) 11 Page - Analog Devices |
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AD5392BCPZ-3 Datasheet(HTML) 11 Page - Analog Devices |
11 / 40 page Data Sheet AD5381 Rev. D | Page 11 of 40 PARALLEL INTERFACE TIMING DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T MIN to TMAX, unless otherwise noted. Table 7. Parameter 1,2,3 Limit at T MIN, TMAX Unit Description t 0 4.5 ns min REG0, REG1, address to WR rising edge setup time t 1 4.5 ns min REG0, REG1, address to WR rising edge hold time t 2 20 ns min CS pulse width low t 3 20 ns min WR pulse width low t 4 0 ns min CS to WR falling edge setup time t 5 0 ns min WR to CS rising edge hold time t 6 4.5 ns min Data to WR rising edge setup time t 7 4.5 ns min Data to WR rising edge hold time t 8 20 ns min WR pulse width high t 9 4 700 ns min Minimum WR cycle time (single-channel write) t 10 4 30 ns max WR rising edge to BUSY falling edge t 11 4, 5 670 ns max BUSY pulse width low (single-channelupdate) t 12 30 ns min WR rising edge to LDAC falling edge t 13 20 ns min LDAC pulse width low t 14 100 ns max BUSY rising edge to DAC output response time t 15 20 ns min LDAC rising edge to WR rising edge t 16 0 ns min BUSY rising edge to LDAC falling edge t 17 100 ns min LDAC falling edge to DAC output response time t 18 8 µs typ DAC output settling time, boost mode off t 19 20 ns min CLR pulse width low t 20 12 µsmax CLR pulse activation time 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with t R = tR = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. 3 See Figure 7. 4 See Figure 29. 5 Measured with the load circuit of Figure 2. |
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