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AKD4352 Datasheet(PDF) 6 Page - Asahi Kasei Microsystems |
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AKD4352 Datasheet(HTML) 6 Page - Asahi Kasei Microsystems |
6 / 13 page ASAHI KASEI [AK4352] M0040-E-02 2000/11 - 6 - SWITCHING CHARACTERISTICS (Ta=25 °C; VDD=1.8 ∼ 3.6V) Parameter Symbol min typ max Units Master Clock Timing 256fs: Pulse Width Low Pulse Width High 384fs: Pulse Width Low Pulse Width High fCLK tCLKL tCLKH fCLK tCLKL tCLKH 2.048 28 28 3.072 23 23 11.2896 16.9344 12.8 19.2 MHz ns ns MHz ns ns LRCK Frequency fs 8 44.1 50 kHz Serial Interface Timing (Note 8) BICK Period BICK Pulse Width Low Pulse Width High BICK rising to LRCK Edge (Note 9) LRCK Edge to BICK rising (Note 9) SDATA Hold Time SDATA Setup Time tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 312.5 100 100 50 50 50 50 ns ns ns ns ns ns ns Reset Timing PD Pulse Width (Note 10) tRST 300 ns Note 8. Refer to the operating overview section “Audio Data Interface”. Note 9. BICK rising edge must not occur at the same time as LRCK edge. Note 10. The AK4352 can be reset by bringing PD = “L” to “H” only upon power up. n Timing Diagram LRCK BICK tBLR tLRB tBCKL tBCKH 50% VDD 50% VDD SDATA 50% VDD tSDH tSDS LSB Audio Data Input Timing tRST 25%VDD PD Reset Timing |
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