Electronic Components Datasheet Search |
|
ADRF6702ACPZ Datasheet(PDF) 4 Page - Analog Devices |
|
ADRF6702ACPZ Datasheet(HTML) 4 Page - Analog Devices |
4 / 36 page ADRF6702 Data Sheet Rev. B | Page 4 of 36 Parameter Test Conditions/Comments Min Typ Max Unit REFERENCE CHARACTERISTICS REFIN, MUXOUT pins REFIN Input Frequency 12 160 MHz REFIN Input Capacitance 4 pF Phase Detector Frequency 20 40 MHz MUXOUT Output Level Low (lock detect output selected) 0.25 V High (lock detect output selected) 2.7 V MUXOUT Duty Cycle 50 % CHARGE PUMP Charge Pump Current Programmable to 250 μA, 500 μA, 750 μA, 1000 μA 500 μA Output Compliance Range 1 2.8 V PHASE NOISE (FREQUENCY = 1850 MHz, fPFD = 38.4 MHz) Closed loop operation (see Figure 35 for loop filter design) 10 kHz offset −110.8 dBc/Hz 100 kHz offset −105.8 dBc/Hz 1 MHz offset −124.6 dBc/Hz 10 MHz offset −150 dBc/Hz Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.27 °rms Reference Spurs fPFD/2 −112 dBc fPFD −84 dBc fPFD × 2 −87 dBc fPFD × 3 −93 dBc fPFD × 4 −90 dBc PHASE NOISE (FREQUENCY = 1960 MHz, fPFD = 38.4 MHz) Closed loop operation (see Figure 35 for loop filter design) 10 kHz offset −108.5 dBc/Hz 100 kHz offset −104.2 dBc/Hz 1 MHz offset −125.1 dBc/Hz 10 MHz offset −149.9 dBc/Hz Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.25 °rms Reference Spurs fPFD/2 −110 dBc fPFD −83 dBc fPFD × 2 −97 dBc fPFD × 3 −91 dBc fPFD × 4 −97 dBc PHASE NOISE (FREQUENCY = 2140 MHz, fPFD = 38.4 MHz) Closed loop operation (see Figure 35 for loop filter design) 10 kHz offset −107.5 dBc/Hz 100 kHz offset −102.7 dBc/Hz 1 MHz offset −126.1 dBc/Hz 10 MHz offset −150.4 dBc/Hz Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.25 °rms Reference Spurs fPFD/2 −111 dBc fPFD −86 dBc fPFD × 2 −88 dBc fPFD × 3 −91 dBc fPFD × 4 −99 dBc RF OUTPUT HARMONICS Measured at RFOUT, frequency = 2140 MHz Second harmonic −47 dBc Third harmonic −74 dBc LO INPUT/OUTPUT LOP, LON Output Frequency Range Divide by 2 circuit in LO path enabled 1550 2150 MHz Divide by 2 circuit in LO path disabled 3100 4300 MHz LO Output Level at 1960 MHz 2× LO or 1× LO mode, into a 50 Ω load, LO buffer enabled 1 dBm LO Input Level Externally applied 2× LO, PLL disabled 0 dBm LO Input Impedance Externally applied 2× LO, PLL disabled 50 Ω |
Similar Part No. - ADRF6702ACPZ |
|
Similar Description - ADRF6702ACPZ |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |