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AKD4395 Datasheet(PDF) 8 Page - Asahi Kasei Microsystems |
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AKD4395 Datasheet(HTML) 8 Page - Asahi Kasei Microsystems |
8 / 26 page ASAHI KASEI [AK4395] MS0040-E-00 2000/7 - 8 - DC CHARACTERISTICS (Ta = 25 °C; AVDD, DVDD = 4.75~5.25V) Parameter Symbol min typ max Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 2.2 - - - - 0.8 V V High-Level Output Voltage (Iout = -100 µA) Low-Level Output Voltage (Iout = 100 µA) VOH VOL DVDD-0.5 - - - - 0.5 V V Input Leakage Current (Note 17) Iin - - ± 10 µA Note: 17. DFS0/CAD0, CKS1/CAD1 and P/S pins have internal pull-down or pull-up devices, nominally 100k Ω. SWITCHING CHARACTERISTICS (Ta = 25 °C; AVDD, DVDD = 4.75~5.25V; C L = 20pF) Parameter Symbol min typ max Units Master Clock Timing Frequency Duty Cycle fCLK dCLK 7.7 40 41.472 60 MHz % LRCK Frequency (Note 18) Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle fsn fsd fsq Duty 30 60 120 45 54 108 216 55 kHz kHz kHz % Serial Interface Timing BICK Period Normal Speed Mode Double Speed Mode Quad Speed Mode BICK Pulse Width Low Pulse Width High BICK “ ↑” to LRCK Edge (Note 19) LRCK Edge to BICK “ ↑” (Note 19) SDATA Hold Time SDATA Setup Time tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fs 1/64fs 1/64fs 30 30 20 20 20 20 ns ns ns ns ns ns ns ns ns Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN High Time CSN “ ↓” to CCLK “↑” CCLK “ ↑” to CSN “↑” tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 50 50 150 50 50 ns ns ns ns ns ns ns ns Reset Timing PDN Pulse Width (Note 20) tPD 150 ns Notes: 18. When the normal/double/quad speed modes are switched, AK4395 should be reset by PDN pin or RSTN bit. 19. BICK rising edge must not occur at the same time as LRCK edge. 20. The AK4395 can be reset by bringing PDN “L” to “H”. When the states of CKS2-0 or DFS1-0 change, the AK4395 should be reset by PDN pin or RSTN bit. |
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