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CDC536DBG4 Datasheet(PDF) 5 Page - Texas Instruments |
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CDC536DBG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 14 page www.ti.com RECOMMENDED OPERATING CONDITIONS (SEE (1)) ELECTRICAL CHARACTERISTICS TIMING REQUIREMENTS CDC536 SCAS378G – APRIL 1994 – REVISED JULY 2004 MIN MAX UNIT VCC Supply voltage 3 3.6 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage 0 5.5 V IOH High-level output current 32 mA IOL Low-level output current 32 mA TA Operating free-air temperature 0 70 °C (1) Unused inputs must be held high or low. over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C PARAMETER TEST CONDITIONS UNIT MIN MAX VIK VCC = 3 V, II = -18 mA 1.2 V VCC = MIN to MAX (1), IOH = -100 µA VCC-0.2 VOH V VCC = 3 V, IOH = -32 mA 2 VCC = 3 V, IOL = 100 µA 0.2 VOL V VCC = 3 V, IOL = 32 mA 0.5 VCC = 0 or MAX (1), VI = 3.6 V ±10 II µA VCC = 3.6 V, VI = VCC or GND ±1 IOZH VCC = 3.6 V, VO = 3 V 10 µA IOZL VCC = 3.6 V, VO = 0 10 µA Outputs high 2 ICC VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs low 2 mA Outputs disabled 2 Ci VI = VCC or GND 6 pF Co VO = VCC or GND 9 pF (1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT When VCO is operating at four times the CLKIN frequency 25 50 fclock Clock frequency MHz When VCO is operating at double the CLKIN frequency 50 100 Input clock duty cycle 40% 60% After SEL 50 After OE ↓ 50 Stabilization time(1) µs After power up 50 After CLKIN 50 (1) Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics table are not applicable. 5 |
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