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AK5383 Datasheet(PDF) 4 Page - Asahi Kasei Microsystems |
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AK5383 Datasheet(HTML) 4 Page - Asahi Kasei Microsystems |
4 / 20 page ASAHI KASEI [AK5383] M0049-E-03 2000/4 - 4 - 14 SCLK I/O Serial Data Clock Pin Data is clocked out on the falling edge of SCLK. Slave mode: SCLK requires more than 48fs clock. Master mode: SCLK outputs a 128fs(DFS="L") or 64fs(DFS="H") clock. SCLK stays "L" during reset. 15 SDATA O Serial Data Output Pin MSB first, 2's complement. SDATA stays "L" during reset. 16 FSYNC I/O Frame Synchronization Signal Pin Slave mode: When "H", the data bits are clocked out on SDATA. In I 2S mode, FSYNC is Don’t care. Master mode: FSYNC outputs 2fs clock. FSYNC stays "L" during reset. 17 MCLK I Master Clock Input Pin 256fs at DFS="L", 128fs at DFS="H". 18 DFS I Double Speed Sampling Mode Pin "L": Normal Speed "H": Double Speed 19 HPFE I High Pass Filter Enable Pin "L": Disable "H": Enable 20 TEST I Test Pin ( pull-down pin) Should be connected to GND. 21 BGND - Substrate Ground Pin, 0V 22 AGND - Analog Ground Pin, 0V 23 VA - Analog Supply Pin, 5V 24 AINR- I Rch Analog negative input Pin 25 AINR+ I Rch Analog positive input Pin 26 VCOMR O Rch Common Voltage Pin, 2.75V 27 GNDR - Rch Reference Ground Pin, 0V 28 VREFR O Rch Reference Voltage Pin, 3.75V Normally connected to GNDR with a 10µF electrolytic capacitor and a 0.1µF ceramic capacitor Note: All digital inputs should not be left floating. |
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