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AK5392 Datasheet(PDF) 4 Page - Asahi Kasei Microsystems |
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AK5392 Datasheet(HTML) 4 Page - Asahi Kasei Microsystems |
4 / 19 page ASAHI KASEI [AK5392] 0188-E-01 1997/11 - 4 - 14 SCLK I/O Serial Data Clock Pin Data is clocked out on the falling edge of SCLK. Slave mode: SCLK requires more than 48fs clock. Master mode: SCLK outputs a 128fs clock. SCLK stays "L" during reset. 15 SDATA O Serial Data Output Pin MSB first, 2's complement. SDATA stays "L" during reset. 16 FSYNC I/O Frame Synchronization Signal Pin Slave mode: When "H", the data bits are clocked out on SDATA. Master mode: FSYNC outputs 2fs clock. FSYNC stays "L" during reset. 17 CLK I Master Clock Input Pin CMODE="H":384fs CMODE="L":256fs 18 CMODE I Master Clock Select Pin "L": CLK=256fs (12.288MHz @fs=48kHz) "H": CLK=384fs (18.432MHz @fs=48kHz) 19 HPFE I High Pass Filter Enable Pin "L": Disable "H": Enable 20 TEST I Test Pin Should be connected DGND. 21 BGND - Substrate Ground Pin, 0V 22 AGND - Analog Ground Pin, 0V 23 VA - Analog Supply Pin, 5V 24 AINR- I Rch Analog negative input Pin 25 AINR+ I Rch Analog positive input Pin 26 VCOMR O Rch Common Voltage Pin, 2.5V 27 GNDR - Rch Reference Ground Pin, 0V 28 VREFR O Rch Reference Voltage Pin, 3.75V Normally connected to GNDR with a 10uF electrolytic capacitor and a 0.1uF ceramic capacitor |
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