ASAHI KASEI

[AK5393]

M0038-E-04

2000/4

- 11 -

OPERATION OVERVIEW

n System Clock Input

The external clocks which are required to operate the AK5393 are MCLK, LRCK(fs), SCLK. MCLK should be

synchronized with LRCK but the phase is free of care. MCLK should be 256fs in normal sampling mode(DFS="L") and

double sampling mode needs 128fs as MCLK. Table 2 illustrates standard audio word rates and corresponding frequencies

used in the AK5393.

As the AK5393 includes the phase detect circuit for LRCK, the AK5393 is reset automatically when the synchronization

is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up.

All external clocks must be present unless RST ="L", otherwise excessive current may result from abnormal operation of

internal dynamic logic.

Speed

Normal(DFS ="L")

Double(DFS ="H")

LRCK (max)

54kHz

108kHz

SCLK

~128fs

~64fs

MCLK

256fs

128fs

Table 1. System Clocks

fs

MCLK

SCLK

32.0kHz

8.1920MHz

4.0960MHz

44.1kHz

11.2896MHz

5.6448MHz

48.0kHz

12.2880MHz

6.1440MHz

96.0kHz

12.2880MHz

6.1440MHz

Table 2. Examples of System Clock Frequency

n Serial Data Interface

The AK5393 supports four serial data formats which can be selected via SMODE1 and SMODE2 pins(Table 3). The data

format is MSB-first, 2's complement.

Figure

SMODE2

SMODE1

Mode

LRCK

Figure 1

L

L

Slave Mode

Lch = H, Rch =L

Figure 2

L

H

Master Mode

Lch =H, Rch =L

Figure 3

H

L

I

Lch =L, Rch =H

Figure 4

H

H

I

Lch =L, Rch =H

Table 3. Serial I/F Format