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SN74HC109DRE4 Datasheet(PDF) 2 Page - Texas Instruments |
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SN74HC109DRE4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 19 page SN54HC109, SN74HC109 DUAL JK POSITIVEEDGETRIGGERED FLIPFLOPS WITH CLEAR AND PRESET SCLS470A − MARCH 2003 − REVISED OCTOBER 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H LX X X L H L LX X X H† H† H H ↑ LL L H H H ↑ H L Toggle H H ↑ LH Q0 Q0 H H ↑ HH H L H H L X X Q0 Q0 † This configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. logic diagram, each flip-flop (positive logic) PRE CLK J CLR Q Q C C C C K TG TG TG TG C C C C C C |
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