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TMS320C6457CGMHA2 Datasheet(PDF) 11 Page - Texas Instruments |
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TMS320C6457CGMHA2 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 217 page  Communications Infrastructure Digital Signal Processor SPRS582B—July 2010 TMS320C6457 2009 Texas Instruments Incorporated www.ti.com 1 TMS320C6457 Features • High-Performance Fixed-Point DSP (C6457) – 1.18-ns, 1-ns, and 0.83-ns Instruction Cycle Time – 850-MHz, 1-GHz, and 1.2-GHz Clock Rate – Eight 32-Bit Instructions/Cycle – 8000 and 9600 MIPS/MMACS (16-Bits) – Case Temperature ›Commercial: » 0ºC to 100ºC (850 MHz) » 0ºC to 100ºC (1 GHz) » 0ºC to 95ºC (1.2 GHz) › Extended: » -40ºC to 100ºC (1 GHz) » -40ºC to 95ºC (1.2 GHz) • TMS320C64x+™ DSP Core – Dedicated SPLOOP Instruction – Compact Instructions (16-Bit) – Instruction Set Enhancements – Exception Handling • TMS320C64x+ Megamodule L1/L2 Memory Architecture: – 256K-Bit (32K-Byte) L1P Program Cache [Direct Mapped] – 256K-Bit (32K-Byte) L1D Data Cache [2-Way Set-Associative] – 16M-Bit (2048K-Byte) L2 Unified Mapped Ram/Cache [Flexible Allocation] › Configurable up to 1MB of L2 Cache – 512K-Bit (64K-Byte) L3 ROM – Time Stamp Counter •Enhanced VCP2 – Supports Over 694 7.95-Kbps AMR – Programmable Code Parameters • Two Enhanced Turbo Decoder Coprocessors (TCP2_A and TCP2_B) – Each TCP2 Supports up to Eight 2-Mbps 3GPP (6 Iterations) – Programmable Turbo Code and Decoding Parameters • Endianess: Little Endian, Big Endian • 64-Bit External Memory Interface (EMIFA) – Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM) and Synchronous Memories (SBSRAM, ZBT SRAM) – Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.) – 32M-Byte Total Addressable External Memory Space • 32-Bit DDR2 Memory Controller (DDR2-667 SDRAM) • Four 1× Serial RapidIO® Links (or One 4×), v1.3 Compliant – 1.25-, 2.5-, 3.125-Gbps Link Rates – Message Passing, DirectIO Support, Error Mgmt Extensions, Congestion Control – IEEE 1149.6 Compliant I/Os • EDMA3 Controller (64 Independent Channels) •32-/16-Bit Host-Port Interface (HPI) • Two 1.8-V McBSPs • 10/100/1000 Mb/s Ethernet MAC (EMAC) – IEEE 802.3 Compliant –Supports SGMII, v1.8 Compliant – 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels • Two 64-Bit General-Purpose Timers – Configurable as Four 32-Bit Timers – Configurable in a Watchdog Timer Mode •UTOPIA – UTOPIA Level 2 Slave ATM Controller – 8-Bit Transmit and Receive Operations up to 50 MHz per Direction – User-Defined Cell Format up to 64 Bytes • One 1.8-V Inter-Integrated Circuit (I2C) Bus • 16 General-Purpose I/O (GPIO) Pins • System PLL and PLL Controller • DDR PLL, Dedicated to DDR2 Memory Controller • Advanced Event Triggering (AET) Compatible • Trace-Enabled Device • Supports IP Security • IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible • 688-Pin Ball Grid Array (BGA) Package (CMH or GMH Suffix), 0.8-mm Ball Pitch • 0.065-μm/7-Level Cu Metal Process (CMOS) • 3.3-V, 1.8-V, 1.1-V I/Os, 1.1-V and 1.2-V Internal |
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