ADT7460 datasheet(10/47 Pages) ONSEMI

Part #	ADT7460

Description	Remote Thermal Monitor and Fan Controller

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Manufacturer	ONSEMI [ON Semiconductor]

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ADT7460

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10

Figure 14. SMBus Address 0x2C (Pin 9 = 0)

ADDR_SEL

ADT7460

9

8

PWM3/

ADDR_EN

10 kW

ADDRESS = 0x2C

Figure 15. SMBus Address 0x2D (Pin 9 = 1)

ADDR_SEL

ADT7460

9

8

PWM3/

ADDR_EN

10 kW

ADDRESS = 0x2D

VCC

Figure 16. Unpredictable SMBus Address if Pin 8

is Unconnected

UNCONNECTED. CAN

CAUSE UNPREDICTABLE

ADDRESSES

NOTE THAT IF THE ADT7460 IS PLACED INTO ADDRESS

SELECT MODE, PINS 8 AND 9 CAN BE USED AS THE

ALTERNATE FUNCTIONS (PWM3, TACH4/THERM) ONLY IF THE

CORRECT CIRCUIT IS MUXED IN AT THE CORRECT TIME.

CARE SHOULD BE TAKEN TO ENSURE THAT PIN 8

(PWM3/ADDR_EN) IS EITHER TIED HIGH OR LOW. LEAVING PIN

8 FLOATING COULD CAUSE THE ADT7460 TO POWERUP WITH

AN UNEXPECTED ADDRESS.

DO NOT LEAVE ADDR_EN

ADDR_SEL

ADT7460

9

8

PWM3/

ADDR_EN

10 kW

VCC

NC

The facility to make hardwired changes to the SMBus

slave address allows the user to avoid conflicts with other

devices sharing the same serial bus, for example, if more

than one ADT7460 is used in a system.

The serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a

start condition, defined as a high-to-low transition

on the serial data line SDA while the serial clock

line SCL remains high. This indicates that an

address/data stream will follow. All slave

peripherals connected to the serial bus respond to

the star condition and shift in the next eight bits,

consisting of a 7-bit address (MSB first) plus a

R/W bit, which determine the direction of the data

transfer, that is, whether data is written to or read

from the slave device.

The peripheral whose address corresponds to the

transmitted address responds by pulling the data

line low during the low period before the ninth

clock pulse, known as the Acknowledge bit. All

other devices on the bus now remain idle while the

selected device waits for data to be read from or

written to it. If the R/W bit is a 0, the master writes

to the slave device. If the R/W bit is a 1, the

master reads from the slave device.

2. Data is sent over the serial bus in sequences of

nine clock pulses, eight bits of data followed by an

Acknowledge bit from the slave device.

Transitions on the data line must occur during the

low period of the clock signal and remain stable

during the high period, as a low-to-high transition

when the clock is high may be interpreted as a stop

signal. The number of data bytes that can be

transmitted over the serial bus in a single read or

write operation is limited only by what the master

and slave devices can handle.

3. When all data bytes have been read or written,

stop conditions are established. In write mode, the

master pulls the data line high during the 10th

clock pulse to assert a stop condition. In read

mode, the master device overrides the

acknowledge bit by pulling the data line high

during the low period before the ninth clock pulse.

This is known as No Acknowledge. The master

then takes the data line low during the low period

before the 10th clock pulse, then high during the

10th clock pulse to assert a stop condition.

Any number of bytes of data may be transferred over the

serial bus in one operation, but it is not possible to mix read

and write in one operation because the type of operation is

determined at the beginning and cannot subsequently be

changed without starting a new operation.

In the case of the ADT7460, write operations contain

either one or two bytes, and read operations contain one

byte.

To write data to one of the device data registers or read

data from it, the address pointer register must be set so that

the correct data register is addressed. Then data can be

written in that register or read from it. The first byte of a

write operation always contains an address that is stored in

the address pointer register. If data is to be written to the

device, the write operation contains a second data byte that

is written to the register selected by the address pointer

register.

This is illustrated in Figure 17. The device address is sent

over the bus followed by R/W being set to 0. This is followed

by two data bytes. The first data byte is the address of the

internal data register to be written to, which is stored in the

address pointer register. The second data byte is the data to

be written to the internal data register.

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