ALD512D

Advanced Linear Devices

4

SERIAL DATA TRANSFER

The ALD521D has an internal 23 bit binary counter that can

be clocked out serially at the end of an analog conversion

cycle, or conversion, in an asynchronous handshake mode

with an external processor. The ALD521D also determines

the sign bit for the ALD500R where a logic 1 is a positive sign

and a logic 0 is a negative sign. This sign bit is the 24th bit

being sent out by the ALD521D.

At the end ofeach conversion, the ALD521D transmits a 24

bit serial word which requires an external processor to send

in 24 serial clock pulses. This 24 bit serial word consists of

content from the 23 bit binary counter with MSB as the first bit,

LSB the 23rd bit, followed by a sign bit as the last bit. A

transition of DV from a high to low state signals a completed

conversion and readiness for the start of the serial data

transfer.

During a conversion, the ALD521D maintains DV in a high or

logic 1 state. When it completes a conversion, the ALD521D

sets the DV to low. Simultaneously, the ALD521D puts the first

bit of the 24 bit binary word (MSB bit) on Dout. For this first

serial bit out, an external processor has a maximum of 5.5

msec to read the data on Dout and send a serial clock pulse

back to the ALD521D. This serial clock consists of a high to

it resets the DV to a high logic 1 state. In addition, it internally

clocks the next serial bit onto Dout and sets the DV to a low

state again.

Similarly, the ALD521D asynchronously transfers the

remainder of the 24 bit serial word to the external processor.

When all 24 serial bits have been clocked out, the ALD521D

resets the DV to a high state, and starts the integration phase

of the conversion. It keeps DV high for the remainder four

phases of the conversion cycle.

For an external processor to interface to the ALD521D, it

needs a minimum of 2 input pins and one output pin dedicated

for the task. The ALD521D has DV (data valid), and Dout (data

external processor can use either an interrupt or data input for

the interface to DV. After the ALD521D sends the first DV high

to low transition, it waits for a maximum of 5.5 milliseconds for

clock is not received during that time, the ALD521D times out

internally, sets the DV to a high state, and starts a new

conversion. For example, if a conversion cycle is equal to 200

msec., DV will not be valid until 200 msec. later. The external

processor can read DV as an interrupt to begin clocking the 24

bit data. The external processor can also sample DV as a data

input or it can synchronize to the A and B outputs of the

ALD521D to determine when the next serial word becomes

available.

INTERFACE TO ALD500R

The ALD521D has A and B outputs that control the four

conversion phases of the ALD500/ALD500R and has Cout as

an input from the ALD500/ALD500R. Note that Cout of the

ALD500/ALD500R must be connected to pin 3 and pin 8 of the

ALD521D.