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S25FL164K0XNHV020 Datasheet(PDF) 10 Page - SPANSION |
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S25FL164K0XNHV020 Datasheet(HTML) 10 Page - SPANSION |
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10 / 85 page  10 S25FL132K and S25FL164K S25FL132K_164K_00_03 October 16, 2013 Data Sheet (Pre limin ar y) 2. General Description The S25FL132K and S25FL164K of non-volatile flash memory devices connect to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (SIngle I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial protocols. This multiple width interface is called SPI Multi-I/O or MIO. The SPI-MIO protocols use only 4 to 6 signals: Chip Select (CS#) Serial Clock (CLK) Serial Data – IO0 (SI) – IO1 (SO) – IO2 (WP#) – IO3 (HOLD#) The SIO protocol uses Serial Input (SI) and Serial Output (SO) for data transfer. The DIO protocols use IO0 and IO1 to input or output two bits of data in each clock cycle. The Write Protect (WP#) input signal option allows hardware control over data protection. Software controlled commands can also manage data protection. The HOLD# input signal option allows commands to be suspended and resumed on any clock cycle. The QIO protocols use all of the data signals (IO0 to IO3) to transfer 4 bits in each clock cycle. When the QIO protocols are enabled the WP# and HOLD# inputs and features are disabled. Clock frequency of up to 108 MHz is supported, allowing data transfer rates up to: Single bit data path = 13.5 Mbytes/s Dual bit data path = 27 Mbytes/s Quad bit data path = 54 Mbytes/s Executing code directly from flash memory is often called eXecute-In-Place or XIP. By using S25FL132K and S25FL164K devices at the higher clock rates supported, with QIO commands, the command read transfer rate can match or exceed traditional x8 or x16 parallel interface, asynchronous, NOR flash memories, while reducing signal count dramatically. The Continuous Read Mode allows for random memory access with as few as 8-clocks of overhead for each access, providing efficient XIP operation. The Wrapped Read mode provides efficient instruction or data cache refill via a fast read of the critical byte that causes a cache miss, followed by reading all other bytes in the same cache line in a single read command. The S25FL132K and S25FL164K: Support JEDEC standard manufacturer and device type identification. Program pages of 256 bytes each. One to 256 bytes can be programmed in each Page Program operation. Pages can be erased in groups of 16 (4-kB aligned sector erase), groups of 256 (64-kB aligned block erase), or the entire chip (chip erase). The S25FL1-K devices operate on a single 2.7V to 3.6V power supply and all devices are offered in space- saving packages. Provides an ideal storage solution for systems with limited space, signal connections, and power. These memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data. |
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