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S25FL164K0XMFI001 Datasheet(PDF) 7 Page - SPANSION

Part # S25FL164K0XMFI001
Description  CMOS 3.0-Volt Flash Non-Volatile Memory Serial Peripheral Interface with Multi-I/O Industrial and Automotive Temperature
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
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S25FL164K0XMFI001 Datasheet(HTML) 7 Page - SPANSION

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October 16, 2013 S25FL132K_164K_00_03
S25FL132K and S25FL164K
7
Da ta
Shee t
(Prelim i nar y )
Figures
Figure 3.1
Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3.2
Bus Master and Memory Devices on the SPI Bus – Single Bit Data Path . . . . . . . . . . . . . . . 17
Figure 3.3
Bus Master and Memory Devices on the SPI Bus – Dual Bit Data Path . . . . . . . . . . . . . . . . 17
Figure 3.4
Bus Master and Memory Devices on the SPI Bus – Quad Bit Data Path . . . . . . . . . . . . . . . 18
Figure 4.1
SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4.2
Stand Alone Instruction Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4.3
Single Bit Wide Input Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4.4
Single Bit Wide Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4.5
Single Bit Wide I/O Command without Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4.6
Single Bit Wide I/O Command with Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4.7
Dual Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4.8
Quad Output Command without Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4.9
Dual I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4.10
Quad I/O Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5.1
Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 5.2
Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 5.3
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 5.4
Input, Output, and Timing Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 5.5
Power-Up Timing and Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 5.6
Power-Down and Voltage Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 5.7
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 5.8
SPI Single Bit Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 5.9
SPI Single Bit Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 5.10
SPI MIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 5.11
Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 5.12
WP# Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9.1
Read Status Register Command Sequence Diagram for 05h and 35h . . . . . . . . . . . . . . . . . 60
Figure 9.2
Read Status Register-3 Command Sequence Diagram for 33h . . . . . . . . . . . . . . . . . . . . . . 60
Figure 9.3
Write Enable (WREN 06h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 9.4
Write Enable for Volatile Status Register Command Sequence . . . . . . . . . . . . . . . . . . . . . . 61
Figure 9.5
Write Disable (WRDI 04h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 9.6
Write Status Registers Command Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 9.7
Page Program Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 9.8
Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 9.9
64 kB Block Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 9.10
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 9.11
Erase / Program Suspend Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 9.12
Erase / Program Resume Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 9.13
Read Data Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 9.14
Fast Read Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 9.15
Fast Read Dual Output Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 9.16
Fast Read Quad Output Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 9.17
Fast Read Dual I/O Command Sequence (Initial command or previous M5-4
≠ 10). . . . . . . 70
Figure 9.18
Fast Read Dual I/O Command Sequence (Previous command set M5-4 = 10) . . . . . . . . . . 70
Figure 9.19
Fast Read Quad I/O Command Sequence (Initial command or previous M5-4
≠10) . . . . . . 71
Figure 9.20
Fast Read Quad I/O Command Sequence (Previous command set M5-4 = 10). . . . . . . . . . 71
Figure 9.21
Set Burst with Wrap Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 9.22
Continuous Read Mode Reset for Fast Read Dual or Quad I/O . . . . . . . . . . . . . . . . . . . . . . 73
Figure 9.23
Deep Power-Down Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 9.24
Release from Deep-Power-Down Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 9.25
Read Electronic Signature (RES ABh) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 9.26
READ_ID (90h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 9.27
Read JEDEC ID Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 9.28
Read SFDP Register Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77


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