ALD500AU/ALD500A/ALD500

Advanced Linear Devices

5

DC ELECTRICAL CHARACTERISTICS

500AU

500A

500

Parameter

Symbol

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Test Conditions

Supply Current

0.6

1.0

0.6

1.0

0.6

1.0

mA

V

Power Dissipation

10

10

10

mW

Positive Supply Range

4.5

5.5

4.5

5.5

4.5

5.5

V

Note 4

Negative Supply Range

-4.5

-5.5

-4.5

-5.5

-4.5

-5.5

V

Note 4

Comparator Logic 1,

44

4

V

Output High

Comparator Logic 0,

0.4

0.4

0.4

V

Output Low

Logic 1, Input High

3.5

3.5

3.5

V

Voltage

Logic 0, Input Low

11

1

V

Voltage

Logic Input Current

0.01

0.01

0.01

µA

Comparator Delay

11

1

µsec

Note 5

NOTES:

1. Integrate time

2. End point linearity at

±1/4, ±1/2, ±3/4 Full Scale after Full Scale adjustment.

4. Contact factory for other power supply operating voltage ranges, including Vsupply =

±3V or Vsupply = ±2.5V.

5. Recommended selection of clock periods of one of the following:

t clk = 0.27

µsec, 0.54µsec, or 1.09µsec

which corresponds to clock frequencies of 3.6864 MHz, 1.8432 MHz, 0.9216 MHz respectively.

~

Figure 3. ALD500 TIMING DIAGRAM

66.667 msec.

123,093

Clock Pulses

Positive Input Signal

Negative Input Signal

66.667 msec.

0.5416

µs

123,093

Clock Pulses

B INPUT

A INPUT

1.8432 MHz Clock

1 Conversion Cycle

Auto Zero

Phase

Input Signal

Integration

Phase

Reference

Voltage

Deintegration

Phase

Integrator Zero

Phase

Auto Zero

Phase

Fixed number

of clock pulses

by design.

Variable

number of

clock pulses.

~

Clock data in

or clock data out

of counters within the

the microcontroller

or fixed logic controller,

as needed.

Fixed period of

approx.1 msec.

max. number of

clock pulses

= 246,185

NOT VALID

Stop counter upon

detection of comparator

output going from high

to low state.

START DEINTEGRATION CYCLE

START INTEGRATION CYCLE

START

CONVERSION

CYCLE

START INTEGRATOR ZERO CYCLE

NOT VALID

REPEAT

CONVERSION

CYCLE