ALD500RAU/ALD500RA/ALD500R

Advanced Linear Devices

3

e. Very high resolution, high accuracy measurements

can be achieved simply and at very low cost.

An inherent benefit of the dual slope converter system is noise

immunity. The input noise spikes are integrated (averaged to

near zero) during the integration periods. Integrating ADCs

are immune to the large conversion errors that plague

successive approximation converters and other high resolution

converters and perform very well in high-noise environments.

The slow conversion speed of the integrating converter provides

inherent noise rejection with at least a 20dB/decade attenuation

rate. Interference signals with frequencies at integral multiples

of the integration period are, theoretically, completely removed.

Integrating converters often establish the integration period to

reject 50/60Hz line frequency interference signals.

The relationship of the integrate and deintegrate (charge

and discharge) of the integrating capacitor values are

shown below:

(integrate cycle)

(1)

(deintegrate cycle)

(2)

Combining equations 1 and 2 results in:

(3)

where:

= An offset voltage used as starting voltage

integrated

Figure 2. Basic Dual-Slope Converter

reference voltage is integrated

Actual data conversion is accomplished in two phases: Input

Signal Integration Phase and Reference Voltage Deintegration

Phase.

The integrator output is initialized to 0V prior to the start of

Input Signal Integration Phase. During Input Signal Integration

input where it is maintained for a fixed integration time period

a digital counter

controlled by a crystal oscillator. The

The Reference Voltage Deintegration Phase is initiated

During

ReferenceVoltage Deintegration Phase, internal analog

switches connect a reference voltage having a polarity opposite

digital counter controlled by the same crystal oscillator used

above is used to start counting clock pulses. The Reference

Voltage Deintegration Phase is maintained until the comparator

output inside the dual slope analog processor changes state,

indicating the integrator has returned to 0V. At that point the

digital counter is stopped. The Deintegration time period

proportional to the magnitude of the applied input voltage.

After the digital counter value has been read, the digital

counter, the integrator, and the auto zero capacitor are all

reset to zero through an Integrator Zero Phase and an Auto

Zero Phase so that the next conversion can begin again. In

practice, this process is usually automated so that analog-to-

digital conversion is continuously updated. The digital control

is handled by a microprocessor or a dedicated logic controller.

The output, in the form of a binary serial word, is read by a

microprocessor or a display adapter when desired.

S1

CINT

VINT

RINT

SWITCH DRIVER

CONTROL

LOGIC

POLARITY CONTROL

REF

SWITCHES

INTEGRATOR

COMPARATOR

PHASE

CONTROL

ANALOG

INPUT

(VIN)

VIN

≈ VFULL SCALE

VIN

≈ 1/2VFULL SCALE

tINT

tDINT

VINT = 4.1V MAX

AB

+

+

-

-

MICROCONTROLLER

(CONTROL LOGIC

+ COUNTER)

VOLTAGE

REFERENCE

COUT

POLARITY

DETECTION

tDINT