AD9249BBCZ-65 datasheet(9/36 Pages) AD

Part #	AD9249BBCZ-65

Description	16 Channel, 14-Bit, 65 MSPS, Serial LVDS, 1.8 V ADC

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Manufacturer	AD [Analog Devices]

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Data Sheet

AD9249

Rev. 0 | Page 9 of 36

TIMING SPECIFICATIONS

Table 5.

Parameter

Description

Limit

Unit

SYNC TIMING REQUIREMENTS

tSSYNC

SYNC to rising edge of CLK+ setup time

0.24

ns typ

tHSYNC

SYNC to rising edge of CLK+ hold time

0.40

ns typ

SPI TIMING REQUIREMENTS

See Figure 50

tDS

Setup time between the data and the rising edge of SCLK

2

ns min

tDH

Hold time between the data and the rising edge of SCLK

2

ns min

tCLK

Period of the SCLK

40

ns min

tS

Setup time between CSB1/CSB2 and SCLK

2

ns min

tH

Hold time between CSB1/CSB2 and SCLK

2

ns min

tHIGH

SCLK pulse width high

10

ns min

tLOW

SCLK pulse width low

10

ns min

tEN_SDIO

Time required for the SDIO pin to switch from an input to an output

relative to the SCLK falling edge (not shown in Figure 50)

10

ns min

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an input

relative to the SCLK rising edge (not shown in Figure 50)

10

ns min

SYNC Timing Diagram

Figure 5. SYNC Input Timing Requirements

SYNC

CLK+

tHSYNC

tSSYNC

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