6

Electrical/Optical Characteristics

0

Parameter

Symbol

Min.

Max.

Unit

Condition

Ref.

Peak Input Power Level

–42

dBm

1 mm POF

Notes 3, 5

Logic HIGH

–44

200

Peak Input Power Level

–20

–0

dBm

1 mm POF,

Note 3

Logic LOW

–22

–2

200

Figs. 7, 8,

|PWD| < 30 ns

9, 10

Supply Current

27

45

mA

High Level Output

4.2

4.7

V

Voltage

Low Level Output Voltage

0.22

0.4

V

Output Rise Time

12

30

ns

Note 3

Output Fall Time

10

30

ns

CL = 10 pF

Note 3

Notes:

2. 1.6 mm below seating plane.

3. In recommended receiver circuit, with an optical signal from the recommended transmitter circuit.

4. Pins 1 and 4 are electrically connected to the conductive housing and are also used for mounting and retaining purposes. It is required that

pin 1 and 4 be connected to ground to maintain conductive housing shield effectiveness.

5. BER

≤10E-9, includes a 10.8 dB margin below the receiver switching threshold level (signal to noise ratio = 12).

5

6

7

8

4

1

BOTTOM VIEW,

HFBR 25x5AZ/BZ

SEE NOTE 4

PIN

FUNCTION

1

4

5

6

7

8

CONNECTED TO PIN 4

CONNECTED TO PIN 1

NO CONNECT

VCC

GND

VO

HFBR-25x5AZ/BZ Receivers

The HFBR-25x5AZ/BZ receiver consists of a silicon PIN photodiode and

digitizing IC to produce a logic compatible output. The IC includes a unique

circuit to correct the pulse width distortion of the first bit after a long idle

period. This enables operation from DC to 10 MBd with low PWD for arbitrary

data patterns. The receiver output is a “push–pull” stage compatible with

TTL and CMOS logic. The receiver housing is a dark grey, conductive plastic.

The HFBR-2505AZ is compatible with SMA connectors, while the HFBR-

Absolute Maximum Ratings

Parameter

Symbol

Min.

Max.

Unit

Reference

Storage and Operating Temperature

–40

85

°C

Supply Voltage

–0.5

+5.5

V

Average Output Current

–16

+16

mA

Output Power Dissipation

80

mW

Lead Soldering Cycle

Temp

260

˚C

Note 2

Time

10

s