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S25FS256SDSNHV303 Datasheet(PDF) 7 Page - SPANSION

Part # S25FS256SDSNHV303
Description  MirrorBit Flash Non-Volatile Memory
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Manufacturer  SPANSION [SPANSION]
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S25FS256SDSNHV303 Datasheet(HTML) 7 Page - SPANSION

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November 6, 2013 S25FS-S_00_04
S25FS-S Family
7
Da ta
Shee t
(Prelim i nar y )
Figures
Figure 3.1
Bus Master and Memory Devices on the SPI Bus - Single Bit Data Path . . . . . . . . . . . . . . . 21
Figure 3.2
Bus Master and Memory Devices on the SPI Bus - Dual Bit Data Path . . . . . . . . . . . . . . . . 22
Figure 3.3
Bus Master and Memory Devices on the SPI Bus - Quad Bit Data Path . . . . . . . . . . . . . . . . 22
Figure 4.1
SPI SDR Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4.2
SPI DDR Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4.3
Stand Alone Instruction Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 4.4
Single Bit Wide Input Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 4.5
Single Bit Wide Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4.6
Single Bit Wide I/O Command without Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4.7
Single Bit Wide I/O Command with Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4.8
Dual I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4.9
Quad I/O Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4.10
Quad I/O Read Command in QPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 4.11
DDR Quad I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 4.12
DDR Quad I/O Read in QPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 5.1
Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 5.2
Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 5.3
Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 5.4
Power-Down and Voltage Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 6.1
Waveform Element Meanings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 6.2
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 6.3
Input, Output, and Timing Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 6.4
Reset Low at the End of POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 6.5
Reset High at the End of POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 6.6
POR Followed by hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 6.7
Hardware Reset when Quad Mode is Not Enabled and IO3 / Reset# is Enabled . . . . . . . . . 39
Figure 6.8
Hardware Reset when Quad Mode and IO3 / Reset# are Enabled . . . . . . . . . . . . . . . . . . . . 40
Figure 6.9
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 6.10
SPI Single Bit Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 6.11
SPI Single Bit Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 6.12
SPI SDR MIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 6.13
WP# Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 6.14
SPI DDR Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 6.15
SPI DDR Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 6.16
SPI DDR Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 7.1
16-Lead SOIC Package (SO3016), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 7.2
SOIC 16-Lead, 300-mil Body Width (SO3016) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 7.3
8-Pin Plastic Small Outline Package (SOIC8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7.4
8-Connector Package (WSON 6x5), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7.5
SOIC 8-Lead, 208 mil Body Width (SOC008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 7.6
WSON 8-Contact 6x5 mm Leadless (WND008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 7.7
WSON 8-Contact 6x8 mm Leadless (WNH008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 7.8
24-Ball BGA, 5x5 Ball Footprint (FAB024), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 7.9
Ball Grid Array 24-Ball 6x8 mm (FAB024) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 7.10
24-Ball BGA, 4x6 Ball Footprint (FAC024), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 7.11
Ball Grid Array 24-Ball 6 x 8 mm (FAC024) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 8.1
OTP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 9.1
Sector Protection Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 9.2
Advanced Sector Protection Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 10.1
Read Identification (RDID) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 10.2
Read Identification (RDID) QPI Mode Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 10.3
Read Quad Identification (RDQID) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 10.4
RSFDP Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 10.5
RSFDP QPI Mode Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93


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