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TPS70950DRVR Datasheet(PDF) 2 Page - Texas Instruments |
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TPS70950DRVR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 28 page TPS709 SBVS186E – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS(1) PRODUCT VOUT XX is the nominal output voltage (for example 28 = 2.8 V). TPS709xxyyyz YYY is the package designator Z is the package quantity; R is for reel (3000 pieces), T is for tape (250 pieces) (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Specified at TJ = –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND. VALUE MIN MAX UNIT VIN –0.3 +32 V Voltage VEN –0.3 +7 V VOUT –0.3 +7 V Maximum output current IOUT Internally limited Output short-circuit duration Indefinite Continuous total power dissipation PDISS See the Thermal Information table Junction, TJ –55 +150 °C Temperature Storage, Tstg –55 +150 °C Human body model (HBM) 2 kV Electrostatic discharge (ESD) ratings Charged device model (CDM) 500 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. THERMAL INFORMATION TPS709xx DBV DCY DRV THERMAL METRIC(1) UNITS (SOT-23) (SOT-223) (SON) 5 PINS 4 PINS 6 PINS θJA Junction-to-ambient thermal resistance 212.1 64.7 73.1 θJCtop Junction-to-case (top) thermal resistance 78.5 47.5 97.0 θJB Junction-to-board thermal resistance 39.5 13.9 42.6 °C/W ψJT Junction-to-top characterization parameter 2.86 6.8 2.9 ψJB Junction-to-board characterization parameter 38.7 13.8 42.9 θJCbot Junction-to-case (bottom) thermal resistance N/A N/A 12.8 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated |
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