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AD7399BRU-REEL7 Datasheet(PDF) 5 Page - Analog Devices

Part # AD7399BRU-REEL7
Description  Quad, Serial-Input 12-Bit/10-Bit DACs
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7399BRU-REEL7 Datasheet(HTML) 5 Page - Analog Devices

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AD7398/AD7399
Rev. C | Page 5 of 24
Parameter
Symbol
Condition
3 V to 5 V ± 10%
±5 V ± 10%
Unit
AC CHARACTERISTICS
Output Slew Rate
SR
Data = 000H to 3FFH to 000H
2
2
V/μs typ
Settling Time8
tS
To ±0.1% of full scale
6
6
μs typ
Shutdown Recovery
tSDR
6
6
μs typ
DAC Glitch
Q
Code 1FFH to 200H to 1FFH
150
150
nVs typ
Digital Feedthrough
QDF
15
15
nVs typ
Feedthrough
VOUT/VREF
VREF = 1.5 VDC + 1 V p-p,
−63
−63
dB typ
data = 000H, f = 100 kHz
SUPPLY CHARACTERISTICS
Shutdown Supply Current
IDD_SD
No load
30/60
30/60
μA typ/max
Positive Supply Current
IDD
VIL = 0 V, no load,
−40°C < TA < +125°C
1.5/2.8
1.6/3
mA typ/max
IDD
VIL = 0 V, no load,
−40°C < TA < +85°C
1.5/2.6
1.6/2.8
mA typ/max
Negative Supply Current
ISS
VIL = 0 V, no load
1.5/2.5
1.6/2.7
mA typ/max
Power Dissipation
PDISS
VIL = 0 V, no load
5
16
mW typ
Power Supply Sensitivity
PSS
ΔVDD = ±5%
0.006
0.006
%/% max
1
One LSB = VREF/1024 V for the 10-bit AD7399.
2
The first two codes (000H and 001H) are excluded from the linearity error measurement in single-supply operation.
3
These parameters are guaranteed by design and not subject to production testing.
4
When VREF is connected to either the VDD or the VSS power supply, the corresponding VOUT voltage programs between ground and the supply voltage minus the offset
voltage of the output buffer, which is the same as the VZSE error specification. See additional discussion in the Theory of Operation section.
5
Input resistance is code dependent.
6
Typicals represent average readings measured at 25°C.
7
All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
8
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
TIMING DIAGRAMS
SDI
tCSS
tDS
tDH
tCH
tCL
tCSH
tLDAC
tLDH
SA
SD
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CLK
IN
REG
LD
tLDS
CS
LDAC
Figure 3. AD7398 Timing Diagram (AD7399 with SDI = 14 Bits Only)
CLK
tCH
tCL
tCSH
tCSS
tLDS
tLDH
tLDS
tLDAC
tCSS
1/
fCLK
CS
LDAC
Figure 4. Continuous Clock Timing Diagram


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