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74V2T126 Datasheet(PDF) 1 Page - STMicroelectronics

Part No. 74V2T126
Description  DUAL BUS BUFFER (3-STATE)
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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June 2003
s
HIGH SPEED: tPD = 3.8ns (TYP.) at VCC =5V
s
LOW POWER DISSIPATION:
ICC =1µA(MAX.) at TA =25°C
s
COMPATIBLE WITH TTL OUTPUTS:
VIH =2V (MIN), VIL =0.8V (MAX)
s
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|= IOL =8mA (MIN)
s
BALANCED PROPAGATION DELAYS:
tPLH tPHL
s
OPERATING VOLTAGE RANGE:
VCC(OPR) = 4.5V to 5.5V
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V2T126 is an advanced high-speed CMOS
DUAL BUS BUFFER fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology.
3-STATE control input nG has to be set LOW to
place the output into the high impedance state.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 3V to 5V systems
and it is ideal for portable applications like
personal digital assistant, camcorder and all
battery-powered equipment.
All
inputs
and
outputs
are
equipped
with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
74V2T126
DUAL BUS BUFFER (3-STATE)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
T & R
SOT23-8L
74V2T126STR
SOT23-8L
Obsolete
Product(s)
- Obsolete
Product(s)




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