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A8182SL Datasheet(PDF) 7 Page - Allegro MicroSystems |
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A8182SL Datasheet(HTML) 7 Page - Allegro MicroSystems |
7 / 8 page 8182 LOW-DROPOUT, 3 V REGULATOR LOAD TRANSIENT PERFORMANCE ENABLE TRANSIENT PERFORMANCE V I = 3.2 V to 6.2 V, CO = 1 µF, IO = 60 mA, TA = 25°C V I = 3.2 V to 6.2 V, CO = 1 µF, TA = 25°C Dwg. WP-026 VO IO 100 mA 1 mA 3.5 V 3.0 V 2.5 V <100 µs <300 µs Dwg. WP-027 VO VE 0 3.0 V 0 <125 µs <250 µs VI The RESET output of the comparator pro- duces a logic low whenever the COMP input is below 1.23 V. An out-of-regulation detector can be configured by dividing down the regulator output (an R/R divider is typical) and connecting it to the COMP input. As tne regulator input is ramped up, the RESET signal becomes valid (low) at approximately V I = 1.3 V. The RESET signal will go high when V C = 1.23 V (VO = 2.46 V with an R/R divider). Comparator hysteresis prevents oscillations under low battery conditions. The RESET open-drain output requires an external pull-up resistor. This can be returned to either the input supply or the regulator output, depending on suystem requirements. Note that the RESET sink current is adds to the battery drain in a low-battery condition. Suggested values range from 100 k Ω to 1 MΩ. RESET should be left unconnected if it is not used. INPUT, COMPARATOR, & OUTPUT RELATIONSHIPS *Comparator input voltage is normally obtained from a resistive divider off of the output. 10 V MAX. 1.23 V V V V * 1.3 V 3.0 V V Dwg. WP-025 C(hys) OUTPUT UNDEFINED I O C OR V TYPICAL CHARACTERISTICS (concluded) |
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