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AK4482 Datasheet(PDF) 8 Page - Asahi Kasei Microsystems |
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AK4482 Datasheet(HTML) 8 Page - Asahi Kasei Microsystems |
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8 / 26 page  [AK4482] MS1408-J-01 2012/05 - 8 - スイッチング特性 (Ta = 25 °C; VDD = 4.75 ∼ 5.25V; CL = 20pF) Parameter Symbol min typ max Unit Master Clock Frequency Duty Cycle fCLK dCLK 2.048 40 11.2896 41.472 60 MHz % LRCK Frequency Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle fsn fsd fsq Duty 8 60 120 45 54 108 216 55 kHz kHz kHz % Audio Interface Timing BICK Period Normal Speed Mode Double/Quad Speed Mode BICK Pulse Width Low Pulse Width High BICK “ ↑” to LRCK Edge (Note 12) LRCK Edge to BICK “ ↑” (Note 12) SDTI Hold Time SDTI Setup Time tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fs 1/64fs 30 30 20 20 20 20 ns ns ns ns ns ns ns ns Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN High Time CSN “ ↓” to CCLK “↑” CCLK “ ↑” to CSN “↑” tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns Reset Timing PDN Pulse Width (Note 13) tPD 150 ns Note 12. この規格値は LRCK のエッジと BICK の “ ↑” が重ならないように規定しています。 Note 13. 電源投入時はPDNを “L” から “H” にすることでリセットがかかります。 |
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