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BR24L04-W Datasheet(PDF) 5 Page - Rohm |
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BR24L04-W Datasheet(HTML) 5 Page - Rohm |
5 / 41 page Technical Note 5/40 www.rohm.com 2009.09 - Rev.D © 2009 ROHM Co., Ltd. All rights reserved. BR24L□□-W Series,BR24S□□□-W Series ●Sync data input / output timing SDA tSU:STA tSU:STO tHD:STA START BIT STOP BIT SCL ○Input read at the rise edge of SCL ○Data output in sync with the fall of SCL Fig.1-(a) Sync data input / output timing Fig.1-(b) Start-stop bit timing SDA Write data (n-th address) Stop condition Start condition SCL tWR ACK D0 Fig.1-(c) Write cycle timing Fig.1-(d) WP timing at write execution tHIGH:WP WP SDA D1 D0 ACK ACK DATA(1) DATA(n) tWR SCL ○At write execution, in the area from the D0 taken clock rise of the first DATA(1), to tWR, set WP=“LOW”. ○By setting WP “HIGH” in the area, write can be cancelled. When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again. Fig.1-(e) WP timing at write cance SCL SDA WP tHD:WP ストップコンディション tWR D1 D0 ACK ACK DATA(1) DATA(n) tSU:WP Stop condition SDA (入力) SDA (出力) tHD:STA tHD:DAT tSU:DAT tBUF tPD tDH tLOW tHIGH tR tF SCL (input) (output) |
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