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MCP2510-ISO Datasheet(PDF) 21 Page - Microchip Technology

Part # MCP2510-ISO
Description  Stand-Alone CAN Controller with SPIInterface
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
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MCP2510-ISO Datasheet(HTML) 21 Page - Microchip Technology

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© 2007 Microchip Technology Inc.
DS21291F-page 21
Receive Message Buffering
The MCP2510 includes two full receive buffers with
multiple acceptance filters for each. There is also a
separate Message Assembly Buffer (MAB) which acts
as a third receive buffer (see Figure 4-1).
Receive Buffers
Of the three Receive Buffers, the MAB is always com-
mitted to receiving the next message from the bus. The
remaining two receive buffers are called RXB0 and
RXB1 and can receive a complete message from the
protocol engine. The MCU can access one buffer while
the other buffer is available for message reception or
holding a previously received message.
The MAB assembles all messages received. These
messages will be transferred to the RXBN buffers (See
Register 4-4 to Register 4-9) only if the acceptance fil-
ter criteria are met.
When a message is moved into either of the receive
buffers the appropriate CANINTF.RXNIF bit is set. This
bit must be cleared by the MCU, when it has completed
processing the message in the buffer, in order to allow
a new message to be received into the buffer. This bit
provides a positive lockout to ensure that the MCU has
finished with the message before the MCP2510
attempts to load a new message into the receive buffer.
If the CANINTE.RXNIE bit is set an interrupt will be gen-
erated on the INT pin to indicate that a valid message
has been received.
Receive Priority
RXB0 is the higher priority buffer and has two message
acceptance filters associated with it. RXB1 is the lower
priority buffer and has four acceptance filters associ-
ated with it. The lower number of acceptance filters
makes the match on RXB0 more restrictive and implies
a higher priority for that buffer. Additionally, the
RXB0CTRL register can be configured such that if
RXB0 contains a valid message, and another valid
message is received, an overflow error will not occur
and the new message will be moved into RXB1 regard-
less of the acceptance criteria of RXB1. There are also
two programmable acceptance filter masks available,
one for each receive buffer (see Section 4.5).
When a message is received, bits <3:0> of the RXBNC-
TRL Register will indicate the acceptance filter number
that enabled reception, and whether the received mes-
sage is a remote transfer request.
The RXBNCTRL.RXM bits set special receive modes.
Normally, these bits are set to 00 to enable reception of
all valid messages as determined by the appropriate
acceptance filters. In this case, the determination of
whether or not to receive standard or extended mes-
sages is determined by the RFXNSIDL.EXIDE bit in the
acceptance filter register. If the RXBNCTRL.RXM bits
are set to 01 or 10, the receiver will accept only mes-
sages with standard or extended identifiers respec-
tively. If an acceptance filter has the RFXNSIDL.EXIDE
bit set such that it does not correspond with the
RXBNCTRL.RXM mode, that acceptance filter is ren-
dered useless. These two modes of RXBNCTRL.RXM
bits can be used in systems where it is known that only
standard or extended messages will be on the bus. If
the RXBNCTRL.RXM bits are set to 11, the buffer will
receive all messages regardless of the values of the
acceptance filters. Also, if a message has an error
before the end of frame, that portion of the message
assembled in the MAB before the error frame will be
loaded into the buffer. This mode has some value in
debugging a CAN system and would not be used in an
actual system environment.
RX0BF and RX1BF Pins
In addition to the INT pin which provides an interrupt
signal to the MCU for many different conditions, the
receive buffer full pins (RX0BF and RX1BF) can be
used to indicate that a valid message has been loaded
into RXB0 or RXB1, respectively.
The RXBNBF full pins can be configured to act as buffer
full interrupt pins or as standard digital outputs. Config-
uration and status of these pins is available via the
BFPCTRL register (Register 4-3). When set to operate
in interrupt mode (by setting BFPCTRL.BxBFE and
BFPCTRL.BxBFM bits to a 1), these pins are active low
and are mapped to the CANINTF.RXNIF bit for each
receive buffer. When this bit goes high for one of the
receive buffers, indicating that a valid message has
been loaded into the buffer, the corresponding RXNBF
pin will go low. When the CANINTF.RXNIF bit is cleared
by the MCU, then the corresponding interrupt pin will
go to the logic high state until the next message is
loaded into the receive buffer.
When used as digital outputs, the BFPCTRL.BxBFM
bits must be cleared to a ‘0’ and BFPCTRL.BxBFE bits
must be set to a ‘1’ for the associated buffer. In this
mode the state of the pin is controlled by the BFPC-
TRL.BxBFS bits. Writting a ‘1’ to the BxBFS bit will
cause a high level to be driven on the assicated buffer
full pin, and a ‘0’ will cause the pin to drive low. When
using the pins in this mode the state of the pin should
be modified only by using the Bit Modify SPI command
to prevent glitches from occuring on either of the buffer
full pins.
The entire contents of the MAB is moved
into the receive buffer once a message is
accepted. This means that regardless of
the type of identifier (standard or extended)
and the number of data bytes received, the
entire receive buffer is overwritten with the
MAB contents. Therefore the contents of
all registers in the buffer must be assumed
to have been modified when any message
is received.

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