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MCP2510-ISO Datasheet(PDF) 15 Page - Microchip Technology |
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MCP2510-ISO Datasheet(HTML) 15 Page - Microchip Technology |
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15 / 80 page  © 2007 Microchip Technology Inc. DS21291F-page 15 MCP2510 3.0 MESSAGE TRANSMISSION 3.1 Transmit Buffers The MCP2510 implements three Transmit Buffers. Each of these buffers occupies 14 bytes of SRAM and are mapped into the device memory maps. The first byte, TXBNCTRL, is a control register associated with the message buffer. The information in this register determines the conditions under which the message will be transmitted and indicates the status of the mes- sage transmission. (see Register 3-2). Five bytes are used to hold the standard and extended identifiers and other message arbitration information (see Register 3- 3 through Register 3-8). The last eight bytes are for the eight possible data bytes of the message to be trans- mitted (see Register 3-8). For the MCU to have write access to the message buffer, the TXBNCTRL.TXREQ bit must be clear, indi- cating that the message buffer is clear of any pending message to be transmitted. At a minimum, the TXBN- SIDH, TXBNSIDL, and TXBNDLC registers must be loaded. If data bytes are present in the message, the TXBNDm registers must also be loaded. If the message is to use extended identifiers, the TXBNEIDm registers must also be loaded and the TXBNSIDL.EXIDE bit set. Prior to sending the message, the MCU must initialize the CANINTE.TXINE bit to enable or disable the gener- ation of an interrupt when the message is sent. The MCU must also initialize the TXBNCTRL.TXP priority bits (see Section 3.2). 3.2 Transmit Priority Transmit priority is a prioritization, within the MCP2510, of the pending transmittable messages. This is inde- pendent from, and not necessarily related to, any prior- itization implicit in the message arbitration scheme built into the CAN protocol. Prior to sending the SOF, the pri- ority of all buffers that are queued for transmission is compared. The transmit buffer with the highest priority will be sent first. For example, if transmit buffer 0 has a higher priority setting than transmit buffer 1, buffer 0 will be sent first. If two buffers have the same priority set- ting, the buffer with the highest buffer number will be sent first. For example, if transmit buffer 1 has the same priority setting as transmit buffer 0, buffer 1 will be sent first. There are four levels of transmit priority. If TXBNC- TRL.TXP<1:0> for a particular message buffer is set to 11, that buffer has the highest possible priority. If TXBNCTRL.TXP<1:0> for a particular message buffer is 00, that buffer has the lowest possible priority. 3.3 Initiating Transmission To initiate message transmission the TXBNC- TRL.TXREQ bit must be set for each buffer to be trans- mitted. This can be done by writing to the register via the SPI interface or by setting the TXNRTS pin low for the particular transmit buffer(s) that are to be transmit- ted. If transmission is initiated via the SPI interface, the TXREQ bit can be set at the same time as the TXP pri- ority bits. When TXBNCTRL.TXREQ is set, the TXBNCTRL.ABTF, TXBNCTRL.MLOA and TXBNCTRL.TXERR bits will be cleared. Setting the TXBNCTRL.TXREQ bit does not initiate a message transmission, it merely flags a message buffer as ready for transmission. Transmission will start when the device detects that the bus is available. The device will then begin transmission of the highest prior- ity message that is ready. When the transmission has completed successfully the TXBNCTRL.TXREQ bit will be cleared, the CAN- INTF.TXNIF bit will be set, and an interrupt will be gen- erated if the CANINTE.TXNIE bit is set. If the message transmission fails, the TXBNC- TRL.TXREQ will remain set indicating that the mes- sage is still pending for transmission and one of the following condition flags will be set. If the message started to transmit but encountered an error condition, the TXBNCTRL. TXERR and the CANINTF.MERRF bits will be set and an interrupt will be generated on the INT pin if the CANINTE.MERRE bit is set. If the mes- sage lost arbitration the TXBNCTRL.MLOA bit will be set. 3.4 TXnRTS Pins The TXNRTS Pins are input pins that can be configured as request-to-send inputs, which provides a secondary means of initiating the transmission of a message from any of the transmit buffers, or as standard digital inputs. Configuration and control of these pins is accomplished using the TXRTSCTRL register (see Register 3-2). The TXRTSCTRL register can only be modified when the MCP2510 is in configuration mode (see Section 9.0). If configured to operate as a request to send pin, the pin is mapped into the respective TXBNCTRL.TXREQ bit for the transmit buffer. The TXREQ bit is latched by the falling edge of the TXNRTS pin. The TXNRTS pins are designed to allow them to be tied directly to the RXNBF pins to automatically initiate a message transmission when the RXNBF pin goes low. The TXNRTS pins have internal pullup resistors of 100 k Ω (nominal). 3.5 Aborting Transmission The MCU can request to abort a message in a specific message buffer by clearing the associated TXBnC- TRL.TXREQ bit. Also, all pending messages can be requested to be aborted by setting the CAN- CTRL.ABAT bit. If the CANCTRL.ABAT bit is set to abort all pending messages, the user MUST reset this bit (typically after the user verifies that all TXREQ bits have been cleared) to continue trasmit messages. The CANCTRL.ABTF flag will only be set if the abort was requested via the CANCTRL.ABAT bit. Aborting a mes- sage by resetting the TXREQ bit does cause the ATBF bit to be set. |
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