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P82B96TDS900 Datasheet(PDF) 7 Page - NXP Semiconductors |
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P82B96TDS900 Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 32 page P82B96_8 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 08 — 10 November 2009 7 of 32 NXP Semiconductors P82B96 Dual bidirectional bus buffer Input logic switching threshold voltages VSx, VSy input logic voltage LOW on normal I2C-bus [4] - 640 600 (see Figure 7)mV VSx, VSy input logic level HIGH threshold on normal I2C-bus [4] 700 650 - (see Figure 8)mV dVSx/dT, dVSy/dT temperature coefficient of input thresholds - −2 - - - mV/K VRx, VRy input logic HIGH level fraction of applied VCC 0.58VCC - - 0.58VCC -V VRx, VRy input threshold fraction of applied VCC - 0.5VCC -- - V VRx, VRy input logic LOW level fraction of applied VCC - - 0.42VCC - 0.42VCC V Logic level threshold difference VSx, VSy input/output logic level difference VSx output LOW at 0.2 mA − V Sx input HIGH maximum [2] 50 85 - 50 - mV Thermal resistance Rth(j-pcb) thermal resistance from junction to printed-circuit board SOT96-1 (SO8); average lead temperature at board interface - 127 - - - K/W Bus release on VCC failure VSx, VSy, VTx, VTy VCC voltage at which all buses are guaranteed to be released - - 1 (see Figure 9)V dV/dT temperature coefficient of guaranteed release voltage - −4 - - - mV/K Buffer response time[5] Tfall delay VSx to VTx, VSy to VTy buffer time delay on falling input between VSx = input switching threshold, and VTx output falling 50 % RTx pull-up = 160 Ω; no capacitive load; VCC =5V -70- - - ns Trise delay VSx to VTx, VSy to VTy buffer time delay on rising input between VSx = input switching threshold, and VTx output reaching 50 % VCC RTx pull-up = 160 Ω; no capacitive load; VCC =5V -90- - - ns Table 5. Characteristics …continued Tamb = +25 °C; voltages are specified with respect to GND with VCC = 5 V, unless otherwise specified. Symbol Parameter Conditions Tamb = +25 °C Tamb = −40 °C to +125 °C[1] Unit Min Typ Max Min Max |
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