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AD7545AUE Datasheet(PDF) 2 Page - Analog Devices

Part # AD7545AUE
Description  CMOS 12-Bit Buffered Multiplying DAC
Download  8 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7545AUE Datasheet(HTML) 2 Page - Analog Devices

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–2–
REV. C
AD7545A–SPECIFICATIONS
VDD = +5 V
VDD = +15 V
Limits
Limits
Parameter
Version
TA = + 25 CTMIN–TMAX
1
TA = + 25 CTMIN–TMAX
1
Units
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
All
12
12
12
12
Bits
Relative Accuracy
K, B, T
±1/2
±1/2
±1/2
±1/2
LSB max
L, C, U
±1/2
±1/2
±1/2
±1/2
LSB max
Endpoint Measurement
Differential Nonlinearity
All
±1
±1
±1
±1
LSB max
All Grades Guaranteed 12-Bit
Monotonic Over Temperature
Gain Error
K, B, T
±3
±4
±3
±4
LSB max
Measured Using Internal RFB.
L, C, U
±1
±2
±1
±2
LSB max
DAC Register Loaded with All 1s.
Gain Temperature Coefficient
2
All
±5
±5
±5
±5
ppm/
°C max
∆Gain/∆Temperature
All
±2
±2
±2
±2
ppm/
°C typ
DC Supply Rejection
2
∆Gain/∆V
DD
All
0.002
0.004
0.002
0.004
% per % max
∆V
DD =
±5%
Output Leakage Current at OUT1
K, L
10
50
10
50
nA max
DB0–DB11 = 0 V;
WR, CS = 0 V
B, C
10
50
10
50
nA max
T, U
10
200
10
200
nA max
DYNAMIC PERFORMANCE
Current Settling Time
2
All
1
1
1
1
µs max
To 1/2 LSB. OUT1 Load = 100
Ω,
CEXT = 13 pF. DAC Output Measured
from Falling Edge of
WR, CS = 0 V.
Propagation Delay
2 (from Digital
Input Change to 90%
of Final Analog Output)
All
200
150
ns max
OUT1 Load = 100
Ω, C
EXT = 13 pF
3
Digital-to-Analog Glitch Impulse
All
5
5
nV sec typ
VREF = AGND. OUT1 Load = 100
Ω,
Alternately Loaded with All 0s and 1s.
AC Feedthrough
2, 4
At OUT1
All
5
5
5
5
mV p-p typ
VREF =
±10 V, 10 kHz Sine Wave
REFERENCE INPUT
Input Resistance
All
10
10
10
10
k
Ω min
Input Resistance TC = –300 ppm/
°C typ
(Pin 19 to GND)
20
20
20
20
k
Ω max
Typical Input Resistance = 15 k
ANALOG OUTPUTS
Output Capacitance
2
COUT1
All
70
70
70
70
pF max
DB0–DB11 = 0 V,
WR, CS = 0 V
COUT1
150
150
150
150
pF max
DB0–DB11 = VDD, WR, CS = 0 V
DIGITAL INPUTS
Input High Voltage
VIH
All
2.4
2.4
13.5
13.5
V min
Input Low Voltage
VIL
All
0.8
0.8
1.5
1.5
V max
Input Current
5
IIN
All
±1
±10
±1
±10
µA max
VIN = 0 or VDD
Input Capacitance
2
DB0–DB11,
WR, CS
All
8
8
8
8
pF max
SWITCHING CHARACTERISTICS2
Chip Select to Write Setup Time
K, B, L, C
100
130
75
85
ns min
See Timing Diagram
tCS
T, U
100
170
75
95
ns min
Chip Select to Write Hold Time
tCH
All
0
0
0
0
ns min
Write Pulse Width
K, B, L, C
100
130
75
85
ns min
tCS
≥ t
WR, TCH
≥ 0
tWR
T, U
100
170
75
95
ns min
Data Setup Time
tDS
All
100
150
60
80
ns min
Data Hold Time
tDH
All
5
5
5
5
ns min
POWER SUPPLY
VDD
All
5
5
15
15
V
±5% For Specified Performance
IDD
All
2
2
2
2
mA max
All Digital Inputs VIL or VIH
100
100
100
100
µA max
All Digital Inputs 0 V or VDD
10
10
10
10
µA typ
All Digital Inputs 0 V or VDD
NOTES
1Temperature range as follows: K, L Versions = 0
°C to +70°C; B, C Versions = –25°C to +85°C; T, U Versions = –55°C to +125°C.
2Sample tested to ensure compliance.
3DB0–DB11 = 0 V to V
DD or VDD to 0 V.
4Feedthrough can be further reduced by connecting the metal lid on the ceramic package to DGND.
6Logic inputs are MOS gates. Typical input current (+25
°C) is less than 1 nA.
Specifications subject to change without notice.
(VREF =
10 V, VOUT1 = O V, AGND = DGND unless otherwise noted)


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