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AD7739BRU Datasheet(PDF) 11 Page - Analog Devices

Part # AD7739BRU
Description  8-Channel, High Throughput, 24-Bit Sigma-Delta ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7739BRU Datasheet(HTML) 11 Page - Analog Devices

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Data Sheet
AD7739
Rev. A | Page 11 of 32
OUTPUT NOISE AND RESOLUTION SPECIFICATION
The AD7739 can be operated with chopping enabled or
disabled, allowing the ADC to be programmed to optimize
either the offset drift performance or the throughput rate and
channel switching time. Noise tables for these two primary
modes of operation are outlined below for a selection of output
rates and settling times.
The AD7739 noise performance depends on the selected
chopping mode, the filter word (FW) value, and the selected
analog input range. The AD7739 noise does not vary
significantly with MCLK frequency.
CHOPPING ENABLED
The first mode, in which the AD7739 is configured with
chopping enabled (chop = 1), provides very low noise with
lower output rates.
Table 5 to Table 7 show the −3 dB frequencies and typical
performance versus the channel conversion time and equivalent
output data rate, respectively.
Table 5 shows the typical output rms noise. Table 6 shows the
typical effective resolution based on rms noise. Table 7 shows
the typical output peak-to-peak resolution, representing values
for which there is no code flicker within a 6-sigma limit. The
peak-to-peak resolutions are not calculated based on rms noise
but on peak-to-peak noise.
These typical numbers are generated from 4096 data samples
acquired in continuous conversion mode with an analog input
voltage set to 0 V and MCLK = 6.144 MHz. The conversion
time is selected via the channel conversion time register.
Table 5. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Enabled
FW
Conversion
Time
Register
Conversion
Time (µs)
Output Data
Rate (Hz)
−3 dB
Frequency
(Hz)
Input Range/RMS Noise (µV)
±2.5 V, +2.5 V
±1.25 V, +1.25 V, ±0.625 V, +0.625 V
127
0xFF
2689
372
200
1.8
1.1
46
0xAE
1001
999
500
2.7
1.7
17
0x91
397
2519
1325
4.8
2.7
10
0x8A
251
3982
2209
9.3
4.7
9
0x89
230
4342
2450
10.8
6.3
2
0x82
84
11838
9500
600
460
Table 6. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled
FW
Conversion
Time
Register
Conversion
Time (µs)
Output Data
Rate (Hz)
−3 dB
Frequency
(Hz)
Input Range/Effective Resolution (Bits)
±2.5 V
+2.5 V
±1.25 V
+1.25 V ±0.625 V +0.625 V
127
0xFF
2689
372
200
21.4
20.4
21.2
20.2
20.2
19.2
46
0xAE
1001
999
500
20.8
19.8
20.5
19.5
19.5
18.5
17
0x91
397
2519
1325
20.0
19.0
19.8
18.8
18.8
17.8
10
0x8A
251
3982
2209
19.0
18.0
19.0
18.0
18.0
17.0
9
0x89
230
4342
2450
18.8
17.8
18.6
17.6
17.6
16.6
2
0x82
84
11838
9500
12.9
11.9
12.4
11.4
11.4
10.4
Table 7. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled
FW
Conversion
Time
Register
Conversion
Time (µs)
Output Data
Rate (Hz)
–3 dB
Frequency
(Hz)
Input Range/Peak-to-Peak Resolution (Bits)
±2.5 V
+2.5 V
±1.25 V
+1.25 V ±0.625 V +0.625 V
127
0xFF
2689
372
200
18.6
17.6
18.3
17.3
17.3
16.3
46
0xAE
1001
999
500
17.9
16.9
17.6
16.6
16.6
15.6
17
0x91
397
2519
1325
17.1
16.1
16.9
15.9
15.9
14.9
10
0x8A
251
3982
2209
16.2
15.2
16.2
15.2
15.2
14.2
9
0x89
230
4342
2450
16.0
15.0
15.8
14.8
14.8
13.8
2
0x82
84
11838
9500
10.7
0.7
9.7
8.7
8.7
7.7


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