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AD7612 Datasheet(PDF) 6 Page - Analog Devices

Part # AD7612
Description  16-Bit, 1.5 LSB INL, 2 MSPS PulSAR ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7612 Datasheet(HTML) 6 Page - Analog Devices

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AD7622
Rev. 0 | Page 6 of 28
1 See the Conversion Control section.
2 All timings for wideband warp mode are the same as warp mode.
3 In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
4 See the Digital Interface section and the RESET section.
5 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
6 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
0
0
1
1
DIVSCLK[0]
Symbol
0
1
0
1
Unit
SYNC to SCLK First Edge Delay Minimum
t18
3
3
3
3
ns
Internal SCLK Period Minimum
t19
8
16
32
64
ns
Internal SCLK Period Maximum
t19
20
40
60
140
ns
Internal SCLK High Minimum
t20
2
8
16
32
ns
Internal SCLK Low Minimum
t21
2
8
16
32
ns
SDOUT Valid Setup Time Minimum
t22
1
5
15
5
ns
SDOUT Valid Hold Time Minimum
t23
0
0.5
10
28
ns
SCLK Last Edge to SYNC Delay Minimum
t24
0
0.5
9
26
ns
BUSY High Width Maximum
Warp Mode
t28
0.64
0.92
1.47
2.57
μs
Normal Mode
t28
0.76
1.04
1.59
2.69
μs
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
500µA
IOL
500µA
IOH
1.4V
TO OUTPUT
PIN
CL
50pF
Figure 3. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF
0.8V
2V
2V
0.8V
0.8V
2V
tDELAY
tDELAY
Figure 4. Voltage Reference Levels for Timing


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