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AD9516-5BCPZ-REEL7 Datasheet(PDF) 3 Page - Analog Devices |
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AD9516-5BCPZ-REEL7 Datasheet(HTML) 3 Page - Analog Devices |
3 / 76 page AD9516-5 Rev. A | Page 3 of 76 REVISION HISTORY 8/11—Rev. 0 to Rev. A Changes to Features, Applications, and General Description..... 1 Changes to CPRSET Pin Resistor Parameter, Table 1 .................. 4 Change to P = 2 DM (2/3) Parameter, Table 2 .............................. 5 Changes Test Conditions/Comments, Table 4 .............................. 6 Moved Table 5 to End of Specifications and Renumbered Sequentially ...................................................................................... 13 Change to Shortest Delay Range Parameter, Test Conditions/Comments, Table 14 .......................................... 13 Moved Timing Diagrams ............................................................... 14 Change to Endnote, Table 16 ......................................................... 15 Change to Caption, Figure 8 .......................................................... 18 Change to Captions, Figure 20 and Figure 21 ............................. 20 Moved Figure 23 and Figure 24..................................................... 21 Added Figure 31; Renumbered Sequentially ............................... 22 Change to Mode 1—Clock Distribution or External VCO < 1600 MHz Section ..........................................................................25 Changes to Mode 2 (High Frequency Clock Distribution)— CLK or External VCO > 1600 MHz; Change to Table 22.......... 26 Change to Charge Pump (CP) Section......................................... 28 Changes to PLL Reference Inputs and Reference Switchover Sections............................................................................................. 29 Changes to Prescaler Section and Table 24.................................. 30 Changes to A and B Counters, Digital Lock Detect (DLD), and Current Source Digital Lock Detect (CSDLD) Sections .... 31 Change to Holdover Section.......................................................... 32 Changes to Automatic/Internal Holdover Mode........................ 34 Changes to Clock Distribution Section........................................ 35 Changes to Channel Dividers—LVDS/CMOS Outputs Section .............................................................................................. 37 Change to the Instruction Word (16 Bits) Section ..................... 45 Change to Figure 53........................................................................ 46 Changes to θJA and ΨJT Parameters, Table 46............................... 48 Changes to Register Address 0x003 and Register Address 0x01C, Table 47................................................. 49 Changes to Register Address 0x003, Table 48 ............................. 52 Changes to Register Address 0x016, Bits[2:0], Table 49 ............ 54 Changes to Register Address 0x01C, Bits[4:3], Table 49 ........... 57 Changes to Register Address 0x191, Register Address 0x194, and Register Address 0x197, Bit 5, Table 53 ................................ 66 Added Frequency Planning Using the AD9516 Section............ 71 Changes to LVPECL Clock Distribution and LVDS Clock Distribution Sections; Changes to Figure 59, Figure 60, and Figure 61...........................................................................................72 1/09—Revision 0: Initial Version |
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