AD9851BRSZRL datasheet(7/24 Pages) AD

Part #	AD9851BRSZRL

Description	CMOS 180 MHz DDS/DAC Synthesizer

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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AD9851

–7–

1

Ch1 200mV

T [

]

Tek Run 4.00GS/s

Sample

M 12.5ns Ch 1

–200mV

D 200ps Runs After

 : 208ps

@ : 1.940ns

TPC 7. Typical CMOS comparator p-p output jitter with

the AD9851 configured as a clock generator, DDS fOUT

the AD9851 configured as a clock generator, DDS f

=

OUT

10.1 MHz, VS

10.1 MHz, V

10.1 MHz, V = 5 V, system clock = 180 MHz, 70 MHz LPF.

S

Graph details the center portion of a rising edge with

scope in delayed trigger mode, 200 ps/div. Cursors show

208 ps p-p jitter.

1

Ch1 200mV

T

[

]

Tek Run 4.00GS/s

Sample

M 12.5ns Ch 1

–200mV

D 200ps Runs After

 : 204ps

@ : 3.672ns

TPC 8. Typical CMOS comparator p-p output jitter with the

AD9851 configured as a clock generator, DDS fOUT

AD9851 configured as a clock generator, DDS f

= 40.1 MHz,

OUT

VS

V

V = 5 V, system clock = 180 MHz, 70 MHz LPF. Graph details

S

the center portion of a rising edge with scope in delayed

trigger mode, 200 ps/div. Cursors show 204 ps p-p jitter.

1

Ch1 200mV

T

[

]

Tek Run 4.00GS/s

Sample

 : 280ps

@ : 2.668ns

M 12.5ns Ch 1

–200mV

D 200ps Runs After

TPC 9. Typical CMOS comparator p-p output

jitter with the AD9851 configured as a clock

generator, DDS fOUT

generator, DDS f

= 70.1 MHz, V

OUT

S

= 70.1 MHz, V

= 70.1 MHz, V = 5 V, system

S

clock = 180 MHz, 70 MHz LPF. Graph details

the center portion of a rising edge with scope

in delayed trigger mode, 200 ps/div. Cursors

show 280 ps p-p jitter.

FREQUENCY OFFSET – Hz

–145

100

1k

10k

100k

–135

–130

–125

–120

–115

–100

AD9851 PHASE NOISE

–140

TPC 10. Output Phase Noise (5.2 MHz AOUT), 6

OUT



REFCLK

Multiplier Enabled, System Clock = 180 MHz, Reference

Clock = 30 MHz

REV. D

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AD9851BRSZRL Datasheet(PDF) 7 Page - Analog Devices

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