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AD9517-0 Datasheet(PDF) 40 Page - Analog Devices |
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AD9517-0 Datasheet(HTML) 40 Page - Analog Devices |
40 / 80 page AD9517-0 Data Sheet Rev. E | Page 40 of 80 PROGRAMMABLE N DELAY REFIN (REF1) REFIN (REF2) CLK CLK REF1 REF2 STATUS STATUS R DIVIDER VCO STATUS PROGRAMMABLE R DELAY REFERENCE SWITCHOVER REF_SEL CPRSET VCP VS GND RSET DISTRIBUTION REFERENCE REFMON CP STATUS LD P, P + 1 PRESCALER A/B COUNTERS N DIVIDER BYPASS LF LOW DROPOUT REGULATOR (LDO) VCO PHASE FREQUENCY DETECTOR LOCK DETECT CHARGE PUMP HOLD 0 1 0 1 DIVIDE BY 2, 3, 4, 5, OR 6 Figure 54. Reference and VCO Status Monitors VCO Calibration The AD9517 on-chip VCO must be calibrated to ensure proper operation over process and temperature. VCO calibration centers the dc voltage at the internal VCO input (at the LF pin) for the selected configuration; this is normally required only during initial configuration and any time the PLL settings change. VCO calibra- tion is controlled by a calibration controller driven by the R divider output. The calibration requires that the input reference clock be present at the REFIN pins, and that the PLL be set up properly to lock the PLL loop. During the first initialization after a power-up or a reset of the AD9517, a VCO calibration sequence is initiated by setting Register 0x018[0] = 1b. This can be done during initial setup, before executing an update registers (Register 0x232[0] = 1b). Subsequent to initial setup, a VCO calibration sequence is initiated by resetting Register 0x018[0] = 0b, executing an update registers operation, setting Register 0x018[0] = 1b, and executing another update registers operation. A readback bit, Bit 6 in Register 0x1F, indicates when a VCO calibration is finished by returning a logic true (that is, 1b). The sequence of operations for the VCO calibration is as follows: 1. Program the PLL registers to the proper values for the PLL loop. Note that that automatic holdover mode must be disabled, and the VCO divider must not be set to “Static.” 2. Ensure that the input reference signal is present. 3. For the initial setting of the registers after a power-up or reset, initiate VCO calibration by setting Register 0x018[0] = 1b. Subsequently, whenever a calibration is desired, set Register 0x018[0] = 0b, update registers; and then set Register 0x018[0] = 1b, update registers. 4. A sync operation is initiated internally, causing the outputs to go to a static state determined by normal sync function operation. 5. The VCO calibrates to the desired setting for the requested VCO frequency. 6. Internally, the SYNC signal is released, allowing outputs to continue clocking. 7. The PLL loop is closed. 8. The PLL locks. A sync is executed during the VCO calibration; therefore, the outputs of the AD9517 are held static during the calibration, which prevents unwanted frequencies from being produced. However, at the end of a VCO calibration, the outputs may resume clocking before the PLL loop is completely settled. The VCO calibration clock divider is set as shown in Table 54 (Register 0x018[2:1]). The calibration divider divides the PFD frequency (reference frequency divided by R) down to the calibration clock. The calibration occurs at the PFD frequency divided by the calibration divider setting. Lower VCO calibration clock frequencies result in longer times for a calibration to be completed. The VCO calibration clock frequency is given by fCAL_CLOCK = fREFIN/(R × cal_div) where: fREFIN is the frequency of the REFIN signal. R is the value of the R divider. cal_div is the division set for the VCO calibration divider (Register 0x018[2:1]). The VCO calibration takes 4400 calibration clock cycles. Therefore, the VCO calibration time in PLL reference clock cycles is given by Time to Calibrate VCO = 4400 × R × cal_div PLL Reference Clock Cycles Table 29. Example Time to Complete a VCO Calibration with Different fREFIN Frequencies fREFIN (MHz) R Divider PFD Time to Calibrate VCO 100 1 100 MHz 88 μs 10 10 1 MHz 8.8 ms 10 100 100 kHz 88 ms |
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