AD9517-0ABCPZ datasheet(30/80 Pages) AD

Part #	AD9517-0ABCPZ

Description	12-Output Clock Generator with Integrated 2.8 GHz VCO

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AD9517-0

Data Sheet

Rev. E | Page 30 of 80

PROGRAMMABLE

N DELAY

REFIN (REF1)

REFIN (REF2)

CLK

REF1

REF2

AD9517-0

STATUS

R

DIVIDER

VCO STATUS

PROGRAMMABLE

R DELAY

REFERENCE

SWITCHOVER

REF_ SEL

CPRSET VCP

VS

GND

RSET

DISTRIBUTION

REFERENCE

REFMON

CP

STATUS

LD

P, P + 1

PRESCALER

A/B

COUNTERS

N DIVIDER

BYPASS

LF

LOW DROPOUT

REGULATOR (LDO)

VCO

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

CHARGE

PUMP

HOLD

OUT0

OUT1

OUT0

OUT1

LVPECL

DIVIDE BY

1 TO 32

OUT2

OUT3

OUT2

OUT3

LVPECL

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

DIVIDE BY

1 TO 32

0

1

DIVIDE BY

2, 3, 4, 5, OR 6

PD

SYNC

RESET

SCLK

SDIO

SDO

CS

DIGITAL

LOGIC

SERIAL

CONTROL

PORT

OUT4 (OUT4A)

OUT4 (OUT4B)

OUT5 (OUT5A)

OUT5 (OUT5B)

OUT6 (OUT6A)

OUT6 (OUT6B)

OUT7 (OUT7A)

OUT7 (OUT7B)

∆T

Figure 44. Internal VCO and Clock Distribution

Internal VCO and Clock Distribution

When using the internal VCO and PLL, the VCO divider must

be employed to ensure that the frequency presented to the channel

dividers does not exceed their specified maximum frequency of

1600 MHz (see Table 3). The internal PLL uses an external loop

filter to set the loop bandwidth. The external loop filter is also

crucial to the loop stability.

When using the internal VCO, it is necessary to calibrate the

VCO (Register 0x018[0]) to ensure optimal performance.

For internal VCO and clock distribution applications, use the

register settings that are shown in Table 24.

Table 24. Settings When Using Internal VCO

Register

Function

0x010[1:0] = 00b

PLL normal operation (PLL on).

0x010 to 0x01D

PLL settings. Select and enable a reference

input; set R, N (P, A, B), PFD polarity, and ICP

according to the intended loop configuration.

0x018[0] = 0b,

0x232[0] = 1b

Reset VCO calibration. This is not required

the first time after power-up, but it must be

performed subsequently.

0x1E0[2:0]

Set VCO divider to divide-by-2, divide-by-3,

divide-by-4, divide-by-5, and divide-by-6.

0x1E1[0] = 0b

Use the VCO divider as the source for the

distribution section.

0x1E1[1] = 1b

Select VCO as the source.

0x018[0] = 1b,

0x232[0] = 1b

Initiate VCO calibration.

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