MTV6N100E

5

Motorola TMOS Power MOSFET Transistor Device Data

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

Figure 10. Stored Charge

Figure 11. Diode Forward Voltage versus Current

0

5

IS = 6 A

dlS/dt = 100 A/

µs

VDD = 25 V

TJ = 25°C

2

ID, DRAIN CURRENT (AMPS)

1

3

0

6

1000

100

10

0

10

100

RG, GATE RESISTANCE (OHMS)

4

5

VDD = 480 V

ID = 6 A

VGS = 10 V

TJ = 25°C

tr

tf

td(off)

td(on)

QG, TOTAL GATE CHARGE (nC)

70

0

10

20

40

60

ID = 6 A

TJ = 25°C

VDS

VGS

Q1

Q2

QT

Q3

30

50

10

6

2

0

16

8

4

14

12

400

350

300

250

200

150

50

100

0

VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

0.50

0.70

0.78

0.82

0

4

6

VGS = 0 V

TJ = 25°C

2

0.66

0.74

0.58

0.54

0.62

5

3

1

2

1

3

4

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain–to–source voltage and

drain current that a transistor can handle safely when it is for-

ward biased. Curves are based upon maximum peak junc-

tion temperature and a case temperature (TC) of 25°C. Peak

repetitive pulsed power limits are determined by using the

thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal Resistance–General

Data and Its Use.”

Switching between the off–state and the on–state may tra-

verse any load line provided neither rated peak current (IDM)

nor rated voltage (VDSS) is exceeded and the transition time

(tr,tf) do not exceed 10 µs. In addition the total power aver-

aged over a complete switching cycle must not exceed

(TJ(MAX) – TC)/(R

θJC).

A Power MOSFET designated E–FET can be safely used

in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis-

sipated in the transistor while in avalanche must be less than

the rated limit and adjusted for operating conditions differing

from those specified. Although industry practice is to rate in

terms of energy, avalanche energy capability is not a con-

stant. The energy rating decreases non–linearly with an in-

crease of peak current in avalanche and peak junction

temperature.

Although many E–FETs can withstand the stress of drain–

to–source avalanche at currents up to rated pulsed current

(IDM), the energy rating is specified at rated continuous cur-

rent (ID), in accordance with industry custom. The energy rat-

ing must be derated for temperature as shown in the

accompanying graph (Figure 12). Maximum energy at cur-

rents below rated continuous ID can safely be assumed to

equal the values indicated.