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ADuC7036CCPZ-RL Datasheet(PDF) 7 Page - Analog Devices |
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ADuC7036CCPZ-RL Datasheet(HTML) 7 Page - Analog Devices |
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7 / 132 page  ADuC7036 Rev. C | Page 7 of 132 Parameter Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS1 All logic inputs VINL, Input Low Voltage 0.4 V VINH, Input High Voltage 2 V CRYSTAL OSCILLATOR1 Logic Inputs, XTAL1 Only VINL, Input Low Voltage 0.8 V VINH, Input High Voltage 1.7 V XTAL1 Capacitance 12 pF XTAL2 Capacitance 12 pF ON-CHIP OSCILLATORS Low Power Oscillator 131.072 kHz Accuracy27 Includes drift data from 1000 hour life test −3 +3 % Precision Oscillator 131.072 kHz Accuracy Includes drift data from 1000 hour life test −1 +1 % MCU CLOCK RATE Eight programmable core clock selections within this range (binary divisions 1, 2, 4, 8,…64, 128) 0.16 10.24 20.48 MHz MCU START-UP TIME At Power-On Includes kernel power-on execution time 25 ms After Reset Event Includes kernel power-on execution time 5 ms From MCU Power-Down Oscillator Running Wake Up from Interrupt 2 ms Wake Up from LIN 2 ms Crystal Powered Down Wake Up from Interrupt 500 ms Internal PLL Lock Time 1 ms LIN INPUT/OUTPUT GENERAL Baud Rate 1000 20,000 Bits/sec VDD Supply voltage range at which the LIN interface is functional 7 18 V Input Capacitance 5.5 pF Input Leakage Current Input (low) = IO_VSS −800 −400 μA LIN Comparator Response Time1 Using 22 Ω resistor 38 90 μs ILIN_DOM_MAX Current limit for driver when LIN bus is in dominant state, VBAT = VBAT (max) 40 200 mA ILIN_PAS_REC Driver off, 7 V < VLIN < 18 V, VDD = VLIN − 0.7 V −20 +20 μA ILIN1 VBAT disconnected, VDD = 0 V, 0 < VLIN < 18 V 10 μA ILIN_PAS_DOM1 Input leakage VLIN = 0 V −1 mA ILIN_NO_GND28 Control unit disconnected from ground, GND = VDD, 0 V < VLIN < 18 V, VBAT = 12 V −1 +1 mA VLIN_DOM1 LIN receiver dominant state, VDD > 7 V 0.4 VDD V VLIN_REC1 LIN receiver recessive state, VDD > 7 V 0.6 VDD V VLIN_CNT1 LIN receiver center voltage, VDD > 7 V 0.475 VDD 0.5 VDD 0.525 VDD V VHYS1 LIN receiver hysteresis voltage 0.175 VDD V VLIN_DOM_DRV_LOSUP1 LIN dominant output voltage, VDD = 7 V RLOAD = 500 Ω 1.2 V RLOAD = 1000 Ω 0.6 V VLIN_DOM_DRV_HISUP1 LIN dominant output voltage, VDD = 18 V RLOAD = 500 Ω 2 V RLOAD = 1000 Ω 0.8 V VLIN_RECESSIVE LIN recessive output voltage 0.8 VDD V VBAT Shift28 0 0.1 VDD V GND Shift28 0 0.1 VDD V |
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