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ADUM1301 Datasheet(PDF) 9 Page - Analog Devices |
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ADUM1301 Datasheet(HTML) 9 Page - Analog Devices |
9 / 32 page Data Sheet ADuM1300/ADuM1301 Rev. I | Page 9 of 32 Parameter Symbol Min Typ Max Unit Test Conditions 90 Mbps (CRW Grade Only) VDD1 Supply Current IDD1 (90) 5 V/3 V Operation 43 57 mA 45 MHz logic signal freq. 3 V/5 V Operation 24 36 mA 45 MHz logic signal freq. VDD2 Supply Current IDD2 (90) 5 V/3 V Operation 16 23 mA 45 MHz logic signal freq. 3 V/5 V Operation 29 37 mA 45 MHz logic signal freq. For All Models Input Currents IIA, IIB, IIC, IE1, IE2 −10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 Logic High Input Threshold VIH, VEH 5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V Logic Low Input Threshold VIL, VEL 5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V Logic High Output Voltages VOAH, VOBH, VOCH (VDD1 or VDD2) − 0.1 (VDD1 or VDD2) V IOx = −20 μA, VIx = VIxH (VDD1 or VDD2) − 0.4 (VDD1 or VDD2) − 0.2 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL, VOCL 0.0 0.1 V IOx = 20 μA, VIx = VIxL 0.04 0.1 V IOx = 400 μA, VIx = VIxL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM130xARW Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 50 70 100 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 50 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching6 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels ADuM130xBRW Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 15 35 50 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 6 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional Channels6 tPSKCD 3 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Opposing- Directional Channels6 tPSKOD 22 ns CL = 15 pF, CMOS signal levels ADuM130xCRW Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 14 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional Channels6 tPSKCD 2 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Opposing-Directional Channels6 tPSKOD 5 ns CL = 15 pF, CMOS signal levels |
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